drm/komeda: Add irq handling
1. Added irq_handler/irq_enable/irq_disable to komeda_dev_func, then the
Komeda-CORE can control the HW irq via these chip function.
2. Install irq and register irq_handler to system by DRM, so once the IRQ
coming, the handling sequence is:
komeda_kms_irq_handler(int irq, void *data)
/* step 1. call into the CHIP to recognize event */
mdev->funcs->irq_handler(mdev, &evts);
/* step 2. notify the crtc to handle the events */
for (i = 0; i < kms->n_crtcs; i++)
komeda_crtc_handle_event(&kms->crtcs[i], &evts);
v2:
- Move get IRQ number into this change.
- Enable irq before drm_dev_register.
Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
hifive-unleashed-5.2
james qian wang (Arm Technology China)
Liviu Dudau
parent
321e925c58
commit
0dac37bf1c
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@ -9,6 +9,240 @@
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#include "d71_dev.h"
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#include "malidp_io.h"
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static u64 get_lpu_event(struct d71_pipeline *d71_pipeline)
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{
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u32 __iomem *reg = d71_pipeline->lpu_addr;
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u32 status, raw_status;
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u64 evts = 0ULL;
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raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
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if (raw_status & LPU_IRQ_IBSY)
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evts |= KOMEDA_EVENT_IBSY;
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if (raw_status & LPU_IRQ_EOW)
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evts |= KOMEDA_EVENT_EOW;
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if (raw_status & (LPU_IRQ_ERR | LPU_IRQ_IBSY)) {
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u32 restore = 0, tbu_status;
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/* Check error of LPU status */
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status = malidp_read32(reg, BLK_STATUS);
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if (status & LPU_STATUS_AXIE) {
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restore |= LPU_STATUS_AXIE;
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evts |= KOMEDA_ERR_AXIE;
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}
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if (status & LPU_STATUS_ACE0) {
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restore |= LPU_STATUS_ACE0;
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evts |= KOMEDA_ERR_ACE0;
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}
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if (status & LPU_STATUS_ACE1) {
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restore |= LPU_STATUS_ACE1;
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evts |= KOMEDA_ERR_ACE1;
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}
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if (status & LPU_STATUS_ACE2) {
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restore |= LPU_STATUS_ACE2;
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evts |= KOMEDA_ERR_ACE2;
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}
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if (status & LPU_STATUS_ACE3) {
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restore |= LPU_STATUS_ACE3;
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evts |= KOMEDA_ERR_ACE3;
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}
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if (restore != 0)
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malidp_write32_mask(reg, BLK_STATUS, restore, 0);
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restore = 0;
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/* Check errors of TBU status */
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tbu_status = malidp_read32(reg, LPU_TBU_STATUS);
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if (tbu_status & LPU_TBU_STATUS_TCF) {
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restore |= LPU_TBU_STATUS_TCF;
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evts |= KOMEDA_ERR_TCF;
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}
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if (tbu_status & LPU_TBU_STATUS_TTNG) {
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restore |= LPU_TBU_STATUS_TTNG;
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evts |= KOMEDA_ERR_TTNG;
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}
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if (tbu_status & LPU_TBU_STATUS_TITR) {
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restore |= LPU_TBU_STATUS_TITR;
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evts |= KOMEDA_ERR_TITR;
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}
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if (tbu_status & LPU_TBU_STATUS_TEMR) {
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restore |= LPU_TBU_STATUS_TEMR;
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evts |= KOMEDA_ERR_TEMR;
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}
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if (tbu_status & LPU_TBU_STATUS_TTF) {
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restore |= LPU_TBU_STATUS_TTF;
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evts |= KOMEDA_ERR_TTF;
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}
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if (restore != 0)
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malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0);
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}
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malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
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return evts;
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}
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static u64 get_cu_event(struct d71_pipeline *d71_pipeline)
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{
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u32 __iomem *reg = d71_pipeline->cu_addr;
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u32 status, raw_status;
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u64 evts = 0ULL;
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raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
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if (raw_status & CU_IRQ_OVR)
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evts |= KOMEDA_EVENT_OVR;
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if (raw_status & (CU_IRQ_ERR | CU_IRQ_OVR)) {
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status = malidp_read32(reg, BLK_STATUS) & 0x7FFFFFFF;
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if (status & CU_STATUS_CPE)
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evts |= KOMEDA_ERR_CPE;
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if (status & CU_STATUS_ZME)
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evts |= KOMEDA_ERR_ZME;
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if (status & CU_STATUS_CFGE)
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evts |= KOMEDA_ERR_CFGE;
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if (status)
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malidp_write32_mask(reg, BLK_STATUS, status, 0);
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}
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malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
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return evts;
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}
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static u64 get_dou_event(struct d71_pipeline *d71_pipeline)
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{
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u32 __iomem *reg = d71_pipeline->dou_addr;
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u32 status, raw_status;
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u64 evts = 0ULL;
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raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
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if (raw_status & DOU_IRQ_PL0)
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evts |= KOMEDA_EVENT_VSYNC;
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if (raw_status & DOU_IRQ_UND)
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evts |= KOMEDA_EVENT_URUN;
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if (raw_status & (DOU_IRQ_ERR | DOU_IRQ_UND)) {
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u32 restore = 0;
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status = malidp_read32(reg, BLK_STATUS);
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if (status & DOU_STATUS_DRIFTTO) {
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restore |= DOU_STATUS_DRIFTTO;
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evts |= KOMEDA_ERR_DRIFTTO;
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}
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if (status & DOU_STATUS_FRAMETO) {
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restore |= DOU_STATUS_FRAMETO;
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evts |= KOMEDA_ERR_FRAMETO;
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}
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if (status & DOU_STATUS_TETO) {
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restore |= DOU_STATUS_TETO;
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evts |= KOMEDA_ERR_TETO;
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}
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if (status & DOU_STATUS_CSCE) {
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restore |= DOU_STATUS_CSCE;
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evts |= KOMEDA_ERR_CSCE;
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}
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if (restore != 0)
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malidp_write32_mask(reg, BLK_STATUS, restore, 0);
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}
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malidp_write32(reg, BLK_IRQ_CLEAR, raw_status);
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return evts;
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}
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static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32 gcu_status)
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{
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u32 evts = 0ULL;
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if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
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evts |= get_lpu_event(d71_pipeline);
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if (gcu_status & (GLB_IRQ_STATUS_CU0 | GLB_IRQ_STATUS_CU1))
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evts |= get_cu_event(d71_pipeline);
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if (gcu_status & (GLB_IRQ_STATUS_DOU0 | GLB_IRQ_STATUS_DOU1))
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evts |= get_dou_event(d71_pipeline);
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return evts;
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}
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static irqreturn_t
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d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
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{
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struct d71_dev *d71 = mdev->chip_data;
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u32 status, gcu_status, raw_status;
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gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
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if (gcu_status & GLB_IRQ_STATUS_GCU) {
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raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);
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if (raw_status & GCU_IRQ_CVAL0)
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evts->pipes[0] |= KOMEDA_EVENT_FLIP;
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if (raw_status & GCU_IRQ_CVAL1)
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evts->pipes[1] |= KOMEDA_EVENT_FLIP;
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if (raw_status & GCU_IRQ_ERR) {
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status = malidp_read32(d71->gcu_addr, BLK_STATUS);
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if (status & GCU_STATUS_MERR) {
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evts->global |= KOMEDA_ERR_MERR;
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malidp_write32_mask(d71->gcu_addr, BLK_STATUS,
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GCU_STATUS_MERR, 0);
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}
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}
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malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);
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}
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if (gcu_status & GLB_IRQ_STATUS_PIPE0)
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evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status);
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if (gcu_status & GLB_IRQ_STATUS_PIPE1)
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evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);
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return gcu_status ? IRQ_HANDLED : IRQ_NONE;
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}
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#define ENABLED_GCU_IRQS (GCU_IRQ_CVAL0 | GCU_IRQ_CVAL1 | \
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GCU_IRQ_MODE | GCU_IRQ_ERR)
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#define ENABLED_LPU_IRQS (LPU_IRQ_IBSY | LPU_IRQ_ERR | LPU_IRQ_EOW)
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#define ENABLED_CU_IRQS (CU_IRQ_OVR | CU_IRQ_ERR)
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#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR)
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static int d71_enable_irq(struct komeda_dev *mdev)
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{
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struct d71_dev *d71 = mdev->chip_data;
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struct d71_pipeline *pipe;
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u32 i;
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malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,
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ENABLED_GCU_IRQS, ENABLED_GCU_IRQS);
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for (i = 0; i < d71->num_pipelines; i++) {
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pipe = d71->pipes[i];
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malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
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ENABLED_CU_IRQS, ENABLED_CU_IRQS);
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malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
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ENABLED_LPU_IRQS, ENABLED_LPU_IRQS);
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malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
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ENABLED_DOU_IRQS, ENABLED_DOU_IRQS);
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}
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return 0;
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}
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static int d71_disable_irq(struct komeda_dev *mdev)
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{
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struct d71_dev *d71 = mdev->chip_data;
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struct d71_pipeline *pipe;
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u32 i;
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malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);
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for (i = 0; i < d71->num_pipelines; i++) {
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pipe = d71->pipes[i];
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malidp_write32_mask(pipe->cu_addr, BLK_IRQ_MASK,
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ENABLED_CU_IRQS, 0);
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malidp_write32_mask(pipe->lpu_addr, BLK_IRQ_MASK,
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ENABLED_LPU_IRQS, 0);
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malidp_write32_mask(pipe->dou_addr, BLK_IRQ_MASK,
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ENABLED_DOU_IRQS, 0);
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}
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return 0;
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}
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static int d71_reset(struct d71_dev *d71)
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{
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u32 __iomem *gcu = d71->gcu_addr;
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@ -222,6 +456,9 @@ static struct komeda_dev_funcs d71_chip_funcs = {
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.init_format_table = d71_init_fmt_tbl,
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.enum_resources = d71_enum_resources,
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.cleanup = d71_cleanup,
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.irq_handler = d71_irq_handler,
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.enable_irq = d71_enable_irq,
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.disable_irq = d71_disable_irq,
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};
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struct komeda_dev_funcs *
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@ -18,6 +18,24 @@
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#include "komeda_dev.h"
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#include "komeda_kms.h"
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void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
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struct komeda_events *evts)
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{
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struct drm_crtc *crtc = &kcrtc->base;
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u32 events = evts->pipes[kcrtc->master->id];
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if (events & KOMEDA_EVENT_VSYNC)
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drm_crtc_handle_vblank(crtc);
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/* will handle it together with the write back support */
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if (events & KOMEDA_EVENT_EOW)
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DRM_DEBUG("EOW.\n");
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/* will handle it with crtc->flush */
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if (events & KOMEDA_EVENT_FLIP)
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DRM_DEBUG("FLIP Done.\n");
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}
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struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
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};
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@ -53,6 +53,7 @@ static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
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static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *child, *np = dev->of_node;
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struct clk *clk;
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int ret;
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@ -62,6 +63,11 @@ static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
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return PTR_ERR(clk);
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mdev->mclk = clk;
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mdev->irq = platform_get_irq(pdev, 0);
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if (mdev->irq < 0) {
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DRM_ERROR("could not get IRQ number.\n");
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return mdev->irq;
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}
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for_each_available_child_of_node(np, child) {
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if (of_node_cmp(child->name, "pipeline") == 0) {
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@ -13,6 +13,33 @@
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#include "malidp_product.h"
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#include "komeda_format_caps.h"
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#define KOMEDA_EVENT_VSYNC BIT_ULL(0)
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#define KOMEDA_EVENT_FLIP BIT_ULL(1)
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#define KOMEDA_EVENT_URUN BIT_ULL(2)
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#define KOMEDA_EVENT_IBSY BIT_ULL(3)
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#define KOMEDA_EVENT_OVR BIT_ULL(4)
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#define KOMEDA_EVENT_EOW BIT_ULL(5)
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#define KOMEDA_EVENT_MODE BIT_ULL(6)
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#define KOMEDA_ERR_TETO BIT_ULL(14)
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#define KOMEDA_ERR_TEMR BIT_ULL(15)
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#define KOMEDA_ERR_TITR BIT_ULL(16)
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#define KOMEDA_ERR_CPE BIT_ULL(17)
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#define KOMEDA_ERR_CFGE BIT_ULL(18)
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#define KOMEDA_ERR_AXIE BIT_ULL(19)
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#define KOMEDA_ERR_ACE0 BIT_ULL(20)
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#define KOMEDA_ERR_ACE1 BIT_ULL(21)
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#define KOMEDA_ERR_ACE2 BIT_ULL(22)
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#define KOMEDA_ERR_ACE3 BIT_ULL(23)
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#define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
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#define KOMEDA_ERR_FRAMETO BIT_ULL(25)
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#define KOMEDA_ERR_CSCE BIT_ULL(26)
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#define KOMEDA_ERR_ZME BIT_ULL(27)
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#define KOMEDA_ERR_MERR BIT_ULL(28)
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#define KOMEDA_ERR_TCF BIT_ULL(29)
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#define KOMEDA_ERR_TTNG BIT_ULL(30)
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#define KOMEDA_ERR_TTF BIT_ULL(31)
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/* malidp device id */
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enum {
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MALI_D71 = 0,
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@ -39,6 +66,11 @@ struct komeda_product_data {
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struct komeda_dev;
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struct komeda_events {
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u64 global;
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u64 pipes[KOMEDA_MAX_PIPELINES];
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};
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/**
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* struct komeda_dev_funcs
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*
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@ -60,6 +92,17 @@ struct komeda_dev_funcs {
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int (*enum_resources)(struct komeda_dev *mdev);
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/** @cleanup: call to chip to cleanup komeda_dev->chip data */
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void (*cleanup)(struct komeda_dev *mdev);
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/**
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* @irq_handler:
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*
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* for CORE to get the HW event from the CHIP when interrupt happened.
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*/
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irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
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struct komeda_events *events);
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/** @enable_irq: enable irq */
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int (*enable_irq)(struct komeda_dev *mdev);
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/** @disable_irq: disable irq */
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int (*disable_irq)(struct komeda_dev *mdev);
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};
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/**
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@ -81,6 +124,9 @@ struct komeda_dev {
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/** @mck: HW main engine clk */
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struct clk *mclk;
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/** @irq: irq number */
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int irq;
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int n_pipelines;
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struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
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@ -13,6 +13,7 @@
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_irq.h>
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#include <drm/drm_vblank.h>
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#include "komeda_dev.h"
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@ -33,10 +34,31 @@ static int komeda_gem_cma_dumb_create(struct drm_file *file,
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return drm_gem_cma_dumb_create_internal(file, dev, args);
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}
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static irqreturn_t komeda_kms_irq_handler(int irq, void *data)
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{
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struct drm_device *drm = data;
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struct komeda_dev *mdev = drm->dev_private;
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struct komeda_kms_dev *kms = to_kdev(drm);
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struct komeda_events evts;
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irqreturn_t status;
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u32 i;
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/* Call into the CHIP to recognize events */
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memset(&evts, 0, sizeof(evts));
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status = mdev->funcs->irq_handler(mdev, &evts);
|
||||
|
||||
/* Notify the crtc to handle the events */
|
||||
for (i = 0; i < kms->n_crtcs; i++)
|
||||
komeda_crtc_handle_event(&kms->crtcs[i], &evts);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static struct drm_driver komeda_kms_driver = {
|
||||
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
|
||||
DRIVER_PRIME,
|
||||
DRIVER_PRIME | DRIVER_HAVE_IRQ,
|
||||
.lastclose = drm_fb_helper_lastclose,
|
||||
.irq_handler = komeda_kms_irq_handler,
|
||||
.gem_free_object_unlocked = drm_gem_cma_free_object,
|
||||
.gem_vm_ops = &drm_gem_cma_vm_ops,
|
||||
.dumb_create = komeda_gem_cma_dumb_create,
|
||||
|
|
@ -144,12 +166,22 @@ struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev)
|
|||
|
||||
drm_mode_config_reset(drm);
|
||||
|
||||
err = drm_dev_register(drm, 0);
|
||||
err = drm_irq_install(drm, mdev->irq);
|
||||
if (err)
|
||||
goto cleanup_mode_config;
|
||||
|
||||
err = mdev->funcs->enable_irq(mdev);
|
||||
if (err)
|
||||
goto uninstall_irq;
|
||||
|
||||
err = drm_dev_register(drm, 0);
|
||||
if (err)
|
||||
goto uninstall_irq;
|
||||
|
||||
return kms;
|
||||
|
||||
uninstall_irq:
|
||||
drm_irq_uninstall(drm);
|
||||
cleanup_mode_config:
|
||||
drm_mode_config_cleanup(drm);
|
||||
free_kms:
|
||||
|
|
@ -162,7 +194,9 @@ void komeda_kms_detach(struct komeda_kms_dev *kms)
|
|||
struct drm_device *drm = &kms->base;
|
||||
struct komeda_dev *mdev = drm->dev_private;
|
||||
|
||||
mdev->funcs->disable_irq(mdev);
|
||||
drm_dev_unregister(drm);
|
||||
drm_irq_uninstall(drm);
|
||||
component_unbind_all(mdev->dev, drm);
|
||||
komeda_kms_cleanup_private_objs(mdev);
|
||||
drm_mode_config_cleanup(drm);
|
||||
|
|
|
|||
|
|
@ -110,6 +110,9 @@ int komeda_kms_add_private_objs(struct komeda_kms_dev *kms,
|
|||
struct komeda_dev *mdev);
|
||||
void komeda_kms_cleanup_private_objs(struct komeda_dev *mdev);
|
||||
|
||||
void komeda_crtc_handle_event(struct komeda_crtc *kcrtc,
|
||||
struct komeda_events *evts);
|
||||
|
||||
struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);
|
||||
void komeda_kms_detach(struct komeda_kms_dev *kms);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue