soc/tegra: fuse: Add Tegra210 support
Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
Thierry Reding
parent
7e939de1b2
commit
0dc5a0d836
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@ -7,3 +7,4 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += speedo-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += speedo-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += speedo-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += speedo-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += speedo-tegra210.o
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@ -91,6 +91,7 @@ static const struct of_device_id car_match[] __initconst = {
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{ .compatible = "nvidia,tegra114-car", },
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{ .compatible = "nvidia,tegra124-car", },
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{ .compatible = "nvidia,tegra132-car", },
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{ .compatible = "nvidia,tegra210-car", },
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{},
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};
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@ -100,6 +101,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) {
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};
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static const struct of_device_id tegra_fuse_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
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#endif
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@ -45,7 +45,8 @@
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#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
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defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_132_SOC)
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defined(CONFIG_ARCH_TEGRA_132_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC)
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static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
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{
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return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
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@ -141,3 +142,16 @@ const struct tegra_fuse_soc tegra124_fuse_soc = {
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.info = &tegra124_fuse_info,
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};
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#endif
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#if defined(CONFIG_ARCH_TEGRA_210_SOC)
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static const struct tegra_fuse_info tegra210_fuse_info = {
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.read = tegra30_fuse_read,
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.size = 0x300,
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};
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const struct tegra_fuse_soc tegra210_fuse_soc = {
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.init = tegra30_fuse_init,
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.speedo_init = tegra210_init_speedo_data,
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.info = &tegra210_fuse_info,
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};
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#endif
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@ -81,6 +81,10 @@ void tegra114_init_speedo_data(struct tegra_sku_info *sku_info);
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void tegra124_init_speedo_data(struct tegra_sku_info *sku_info);
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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void tegra210_init_speedo_data(struct tegra_sku_info *sku_info);
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#endif
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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extern const struct tegra_fuse_soc tegra20_fuse_soc;
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#endif
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@ -97,4 +101,8 @@ extern const struct tegra_fuse_soc tegra114_fuse_soc;
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extern const struct tegra_fuse_soc tegra124_fuse_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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extern const struct tegra_fuse_soc tegra210_fuse_soc;
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#endif
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#endif
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@ -0,0 +1,184 @@
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/*
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* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define CPU_PROCESS_CORNERS 2
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#define GPU_PROCESS_CORNERS 2
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#define SOC_PROCESS_CORNERS 3
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#define FUSE_CPU_SPEEDO_0 0x014
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#define FUSE_CPU_SPEEDO_1 0x02c
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#define FUSE_CPU_SPEEDO_2 0x030
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#define FUSE_SOC_SPEEDO_0 0x034
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#define FUSE_SOC_SPEEDO_1 0x038
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#define FUSE_SOC_SPEEDO_2 0x03c
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#define FUSE_CPU_IDDQ 0x018
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#define FUSE_SOC_IDDQ 0x040
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#define FUSE_GPU_IDDQ 0x128
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#define FUSE_FT_REV 0x028
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
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{ 2119, UINT_MAX },
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{ 2119, UINT_MAX },
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};
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static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
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{ UINT_MAX, UINT_MAX },
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{ UINT_MAX, UINT_MAX },
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};
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static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
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{ 1950, 2100, UINT_MAX },
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{ 1950, 2100, UINT_MAX },
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};
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static u8 __init get_speedo_revision(void)
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{
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return tegra_fuse_read_spare(4) << 2 |
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tegra_fuse_read_spare(3) << 1 |
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tegra_fuse_read_spare(2) << 0;
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}
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static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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u8 speedo_rev, int *threshold)
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{
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int sku = sku_info->sku_id;
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/* Assign to default */
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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sku_info->gpu_speedo_id = 0;
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*threshold = THRESHOLD_INDEX_0;
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switch (sku) {
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case 0x00: /* Engineering SKU */
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case 0x01: /* Engineering SKU */
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case 0x07:
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case 0x17:
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case 0x27:
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if (speedo_rev >= 2)
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sku_info->gpu_speedo_id = 1;
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break;
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case 0x13:
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if (speedo_rev >= 2)
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sku_info->gpu_speedo_id = 1;
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sku_info->cpu_speedo_id = 1;
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break;
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default:
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pr_err("Tegra210: unknown SKU %#04x\n", sku);
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/* Using the default for the error case */
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break;
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}
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}
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static int get_process_id(int value, const u32 *speedos, unsigned int num)
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{
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unsigned int i;
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for (i = 0; i < num; i++)
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if (value < speedos[num])
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return i;
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return -EINVAL;
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}
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void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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int cpu_speedo[3], soc_speedo[3], cpu_iddq, gpu_iddq, soc_iddq;
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unsigned int index;
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u8 speedo_revision;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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/* Read speedo/IDDQ fuses */
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cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
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cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
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cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
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soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
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soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
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soc_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
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cpu_iddq = tegra_fuse_read_early(FUSE_CPU_IDDQ) * 4;
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soc_iddq = tegra_fuse_read_early(FUSE_SOC_IDDQ) * 4;
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gpu_iddq = tegra_fuse_read_early(FUSE_GPU_IDDQ) * 5;
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/*
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* Determine CPU, GPU and SoC speedo values depending on speedo fusing
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* revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
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*/
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speedo_revision = get_speedo_revision();
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pr_info("Speedo Revision %u\n", speedo_revision);
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if (speedo_revision >= 3) {
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sku_info->cpu_speedo_value = cpu_speedo[0];
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sku_info->gpu_speedo_value = cpu_speedo[2];
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sku_info->soc_speedo_value = soc_speedo[0];
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} else if (speedo_revision == 2) {
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sku_info->cpu_speedo_value = (-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
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sku_info->gpu_speedo_value = (-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
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sku_info->soc_speedo_value = ( -705 + (1037 * soc_speedo[0] / 100)) / 10;
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} else {
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sku_info->cpu_speedo_value = 2100;
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sku_info->gpu_speedo_value = cpu_speedo[2] - 75;
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sku_info->soc_speedo_value = 1900;
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}
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if ((sku_info->cpu_speedo_value <= 0) ||
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(sku_info->gpu_speedo_value <= 0) ||
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(sku_info->soc_speedo_value <= 0)) {
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WARN(1, "speedo value not fused\n");
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return;
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}
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rev_sku_to_speedo_ids(sku_info, speedo_revision, &index);
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sku_info->gpu_process_id = get_process_id(sku_info->gpu_speedo_value,
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gpu_process_speedos[index],
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GPU_PROCESS_CORNERS);
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sku_info->cpu_process_id = get_process_id(sku_info->cpu_speedo_value,
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cpu_process_speedos[index],
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CPU_PROCESS_CORNERS);
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sku_info->soc_process_id = get_process_id(sku_info->soc_speedo_value,
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soc_process_speedos[index],
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SOC_PROCESS_CORNERS);
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pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
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sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
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}
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@ -22,6 +22,7 @@
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#define TEGRA114 0x35
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#define TEGRA124 0x40
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#define TEGRA132 0x13
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#define TEGRA210 0x21
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#define TEGRA_FUSE_SKU_CALIB_0 0xf0
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#define TEGRA30_FUSE_SATA_CALIB 0x124
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@ -49,8 +50,9 @@ struct tegra_sku_info {
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int cpu_iddq_value;
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int core_process_id;
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int soc_speedo_id;
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int gpu_speedo_id;
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int soc_speedo_value;
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int gpu_process_id;
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int gpu_speedo_id;
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int gpu_speedo_value;
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enum tegra_revision revision;
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};
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