Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie. Small fixes for (mostly Nouveau, some radeon) regressions. * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/nouveau: use the correct fence implementation for nv50 drm/radeon: add new SI pci id radeon: add AGPMode 1 quirk for RV250 drm/radeon: properly track the crtc not_enabled case evergreen_mc_stop() drm/nouveau/bios: fix DCB v1.5 parsing drm/nouveau: add missing pll_calc calls drm/nouveau: fix crash with noaccel=1 drm/nv40: allocate ctxprog with kmalloc drm/nvc0/disp: fix thinko in vblank regression fix..
This commit is contained in:
commit
0e0f092ef0
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@ -49,13 +49,7 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
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if (chan->vblank.crtc != crtc)
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continue;
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if (nv_device(priv)->chipset == 0x50) {
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nv_wr32(priv, 0x001704, chan->vblank.channel);
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nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
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bar->flush(bar);
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nv_wr32(priv, 0x001570, chan->vblank.offset);
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nv_wr32(priv, 0x001574, chan->vblank.value);
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} else {
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if (nv_device(priv)->chipset >= 0xc0) {
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nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
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bar->flush(bar);
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nv_wr32(priv, 0x06000c,
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@ -63,6 +57,17 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
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nv_wr32(priv, 0x060010,
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lower_32_bits(chan->vblank.offset));
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nv_wr32(priv, 0x060014, chan->vblank.value);
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} else {
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nv_wr32(priv, 0x001704, chan->vblank.channel);
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nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
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bar->flush(bar);
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if (nv_device(priv)->chipset == 0x50) {
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nv_wr32(priv, 0x001570, chan->vblank.offset);
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nv_wr32(priv, 0x001574, chan->vblank.value);
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} else {
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nv_wr32(priv, 0x060010, chan->vblank.offset);
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nv_wr32(priv, 0x060014, chan->vblank.value);
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}
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}
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list_del(&chan->vblank.head);
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@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
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});
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}
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void
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int
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nv40_grctx_init(struct nouveau_device *device, u32 *size)
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{
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u32 ctxprog[256], i;
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u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
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struct nouveau_grctx ctx = {
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.device = device,
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.mode = NOUVEAU_GRCTX_PROG,
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.data = ctxprog,
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.ctxprog_max = ARRAY_SIZE(ctxprog)
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.ctxprog_max = 256,
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};
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if (!ctxprog)
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return -ENOMEM;
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nv40_grctx_generate(&ctx);
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nv_wr32(device, 0x400324, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(device, 0x400328, ctxprog[i]);
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*size = ctx.ctxvals_pos * 4;
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kfree(ctxprog);
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return 0;
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}
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@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object)
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return ret;
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/* generate and upload context program */
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nv40_grctx_init(nv_device(priv), &priv->size);
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ret = nv40_grctx_init(nv_device(priv), &priv->size);
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if (ret)
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return ret;
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/* No context present currently */
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nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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@ -15,7 +15,7 @@ nv44_graph_class(void *priv)
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return !(0x0baf & (1 << (device->chipset & 0x0f)));
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}
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void nv40_grctx_init(struct nouveau_device *, u32 *size);
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int nv40_grctx_init(struct nouveau_device *, u32 *size);
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void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
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#endif
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@ -175,14 +175,18 @@ nv_mo32(void *obj, u32 addr, u32 mask, u32 data)
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return temp;
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}
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static inline bool
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nv_strncmp(void *obj, u32 addr, u32 len, const char *str)
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static inline int
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nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
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{
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unsigned char c1, c2;
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while (len--) {
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if (nv_ro08(obj, addr++) != *(str++))
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return false;
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c1 = nv_ro08(obj, addr++);
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c2 = *(str++);
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if (c1 != c2)
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return c1 - c2;
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}
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return true;
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return 0;
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}
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#endif
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@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
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int clk, struct nouveau_pll_vals *);
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int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
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struct nouveau_pll_vals *);
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int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
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int clk, struct nouveau_pll_vals *);
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#endif
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@ -64,7 +64,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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}
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} else
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if (*ver >= 0x15) {
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if (!nv_strncmp(bios, dcb - 7, 7, "DEV_REC")) {
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if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
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u16 i2c = nv_ro16(bios, dcb + 2);
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*hdr = 4;
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*cnt = (i2c - dcb) / 10;
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@ -66,6 +66,24 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
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return ret;
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}
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int
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nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
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int clk, struct nouveau_pll_vals *pv)
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{
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int ret, N, M, P;
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ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P);
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if (ret > 0) {
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pv->refclk = info->refclk;
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pv->N1 = N;
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pv->M1 = M;
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pv->log2P = P;
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}
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return ret;
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}
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static int
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nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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@ -80,6 +98,7 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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return ret;
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priv->base.pll_set = nva3_clock_pll_set;
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priv->base.pll_calc = nva3_clock_pll_calc;
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return 0;
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}
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@ -79,6 +79,7 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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return ret;
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priv->base.pll_set = nvc0_clock_pll_set;
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priv->base.pll_calc = nva3_clock_pll_calc;
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return 0;
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}
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@ -241,6 +241,10 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
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if (unlikely(!abi16))
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return -ENOMEM;
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if (!drm->channel)
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return nouveau_abi16_put(abi16, -ENODEV);
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client = nv_client(abi16->client);
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if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
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@ -129,7 +129,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
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/* initialise synchronisation routines */
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if (device->card_type < NV_10) ret = nv04_fence_create(drm);
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else if (device->chipset < 0x84) ret = nv10_fence_create(drm);
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else if (device->card_type < NV_50) ret = nv10_fence_create(drm);
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else if (device->chipset < 0x84) ret = nv50_fence_create(drm);
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else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
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else ret = nvc0_fence_create(drm);
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if (ret) {
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@ -1330,6 +1330,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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break;
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udelay(1);
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}
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} else {
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save->crtc_enabled[i] = false;
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}
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}
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@ -69,9 +69,12 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
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/* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
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{ PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
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PCI_VENDOR_ID_DELL, 0x00e3, 2},
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/* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */
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/* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
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PCI_VENDOR_ID_DELL, 0x0149, 1},
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/* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
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PCI_VENDOR_ID_IBM, 0x0531, 1},
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/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
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0x1025, 0x0061, 1},
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@ -210,6 +210,7 @@
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{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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