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gpu: host1x: Use correct semantics for HOST1X_CHANNEL_DMAEND 

The HOST1X_CHANNEL_DMAEND is an offset relative to the value written to
the HOST1X_CHANNEL_DMASTART register, but it is currently treated as an
absolute address. This can cause SMMU faults if the CDMA fetches past a
pushbuffer's IOMMU mapping.

Properly setting the DMAEND prevents the CDMA from fetching beyond that
address and avoid such issues. This is currently not observed because a
whole (almost) page of essentially scratch space absorbs any excessive
prefetching by CDMA. However, changing the number of slots in the push
buffer can trigger these SMMU faults.

Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Thierry Reding 2019-02-01 14:28:29 +01:00
parent 8de896eb20
commit 0e43b8da15
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/host1x/hw/cdma_hw.c
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@ -75,7 +75,7 @@ static void cdma_start(struct host1x_cdma *cdma)
cdma->last_pos = cdma->push_buffer.pos;
start = cdma->push_buffer.dma;
end = start + cdma->push_buffer.size + 4;
end = cdma->push_buffer.size + 4;
host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,
HOST1X_CHANNEL_DMACTRL);
@ -126,7 +126,7 @@ static void cdma_timeout_restart(struct host1x_cdma *cdma, u32 getptr)
HOST1X_CHANNEL_DMACTRL);
start = cdma->push_buffer.dma;
end = start + cdma->push_buffer.size + 4;
end = cdma->push_buffer.size + 4;
/* set base, end pointer (all of memory) */
host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART);