Merge branches 'dma-omap', 'dma-pl08x' and 'dma-sa11x0' into dmaengine
Russell King
commit
0e52d987c0
|
|
@ -120,182 +120,156 @@ struct pl08x_channel_data spear300_dma_info[] = {
|
|||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -205,182 +205,156 @@ struct pl08x_channel_data spear310_dma_info[] = {
|
|||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart2_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart2_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart3_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart3_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart4_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart4_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart5_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart5_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -213,182 +213,156 @@ struct pl08x_channel_data spear320_dma_info[] = {
|
|||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c0_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c0_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp1_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c1_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c1_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c2_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c2_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "rs485_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "rs485_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,7 +46,8 @@ struct pl022_ssp_controller pl022_plat_data = {
|
|||
struct pl08x_platform_data pl080_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
.cctl_memcpy =
|
||||
(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
|
||||
|
|
|
|||
|
|
@ -36,336 +36,288 @@ static struct pl08x_channel_data spear600_dma_info[] = {
|
|||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp2_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ext0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
},
|
||||
};
|
||||
|
|
@ -373,7 +325,8 @@ static struct pl08x_channel_data spear600_dma_info[] = {
|
|||
struct pl08x_platform_data pl080_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
.cctl_memcpy =
|
||||
(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
|
||||
|
|
|
|||
|
|
@ -14,8 +14,8 @@
|
|||
#ifndef __PLAT_PL080_H
|
||||
#define __PLAT_PL080_H
|
||||
|
||||
struct pl08x_dma_chan;
|
||||
int pl080_get_signal(struct pl08x_dma_chan *ch);
|
||||
void pl080_put_signal(struct pl08x_dma_chan *ch);
|
||||
struct pl08x_channel_data;
|
||||
int pl080_get_signal(const struct pl08x_channel_data *cd);
|
||||
void pl080_put_signal(const struct pl08x_channel_data *cd, int signal);
|
||||
|
||||
#endif /* __PLAT_PL080_H */
|
||||
|
|
|
|||
|
|
@ -27,9 +27,8 @@ struct {
|
|||
unsigned char val;
|
||||
} signals[16] = {{0, 0}, };
|
||||
|
||||
int pl080_get_signal(struct pl08x_dma_chan *ch)
|
||||
int pl080_get_signal(const struct pl08x_channel_data *cd)
|
||||
{
|
||||
const struct pl08x_channel_data *cd = ch->cd;
|
||||
unsigned int signal = cd->min_signal, val;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -63,18 +62,17 @@ int pl080_get_signal(struct pl08x_dma_chan *ch)
|
|||
return signal;
|
||||
}
|
||||
|
||||
void pl080_put_signal(struct pl08x_dma_chan *ch)
|
||||
void pl080_put_signal(const struct pl08x_channel_data *cd, int signal)
|
||||
{
|
||||
const struct pl08x_channel_data *cd = ch->cd;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lock, flags);
|
||||
|
||||
/* if signal is not used */
|
||||
if (!signals[cd->min_signal].busy)
|
||||
if (!signals[signal].busy)
|
||||
BUG();
|
||||
|
||||
signals[cd->min_signal].busy--;
|
||||
signals[signal].busy--;
|
||||
|
||||
spin_unlock_irqrestore(&lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ config AMBA_PL08X
|
|||
bool "ARM PrimeCell PL080 or PL081 support"
|
||||
depends on ARM_AMBA && EXPERIMENTAL
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Platform has a PL08x DMAC device
|
||||
which can provide DMA engine support
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -78,6 +78,8 @@ struct sa11x0_dma_desc {
|
|||
|
||||
u32 ddar;
|
||||
size_t size;
|
||||
unsigned period;
|
||||
bool cyclic;
|
||||
|
||||
unsigned sglen;
|
||||
struct sa11x0_dma_sg sg[0];
|
||||
|
|
@ -178,19 +180,24 @@ static void noinline sa11x0_dma_start_sg(struct sa11x0_dma_phy *p,
|
|||
return;
|
||||
|
||||
if (p->sg_load == txd->sglen) {
|
||||
struct sa11x0_dma_desc *txn = sa11x0_dma_next_desc(c);
|
||||
if (!txd->cyclic) {
|
||||
struct sa11x0_dma_desc *txn = sa11x0_dma_next_desc(c);
|
||||
|
||||
/*
|
||||
* We have reached the end of the current descriptor.
|
||||
* Peek at the next descriptor, and if compatible with
|
||||
* the current, start processing it.
|
||||
*/
|
||||
if (txn && txn->ddar == txd->ddar) {
|
||||
txd = txn;
|
||||
sa11x0_dma_start_desc(p, txn);
|
||||
/*
|
||||
* We have reached the end of the current descriptor.
|
||||
* Peek at the next descriptor, and if compatible with
|
||||
* the current, start processing it.
|
||||
*/
|
||||
if (txn && txn->ddar == txd->ddar) {
|
||||
txd = txn;
|
||||
sa11x0_dma_start_desc(p, txn);
|
||||
} else {
|
||||
p->txd_load = NULL;
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
p->txd_load = NULL;
|
||||
return;
|
||||
/* Cyclic: reset back to beginning */
|
||||
p->sg_load = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -224,13 +231,21 @@ static void noinline sa11x0_dma_complete(struct sa11x0_dma_phy *p,
|
|||
struct sa11x0_dma_desc *txd = p->txd_done;
|
||||
|
||||
if (++p->sg_done == txd->sglen) {
|
||||
vchan_cookie_complete(&txd->vd);
|
||||
if (!txd->cyclic) {
|
||||
vchan_cookie_complete(&txd->vd);
|
||||
|
||||
p->sg_done = 0;
|
||||
p->txd_done = p->txd_load;
|
||||
p->sg_done = 0;
|
||||
p->txd_done = p->txd_load;
|
||||
|
||||
if (!p->txd_done)
|
||||
tasklet_schedule(&p->dev->task);
|
||||
if (!p->txd_done)
|
||||
tasklet_schedule(&p->dev->task);
|
||||
} else {
|
||||
if ((p->sg_done % txd->period) == 0)
|
||||
vchan_cyclic_callback(&txd->vd);
|
||||
|
||||
/* Cyclic: reset back to beginning */
|
||||
p->sg_done = 0;
|
||||
}
|
||||
}
|
||||
|
||||
sa11x0_dma_start_sg(p, c);
|
||||
|
|
@ -416,27 +431,47 @@ static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan,
|
|||
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
||||
struct sa11x0_dma_dev *d = to_sa11x0_dma(chan->device);
|
||||
struct sa11x0_dma_phy *p;
|
||||
struct sa11x0_dma_desc *txd;
|
||||
struct virt_dma_desc *vd;
|
||||
unsigned long flags;
|
||||
enum dma_status ret;
|
||||
size_t bytes = 0;
|
||||
|
||||
ret = dma_cookie_status(&c->vc.chan, cookie, state);
|
||||
if (ret == DMA_SUCCESS)
|
||||
return ret;
|
||||
|
||||
if (!state)
|
||||
return c->status;
|
||||
|
||||
spin_lock_irqsave(&c->vc.lock, flags);
|
||||
p = c->phy;
|
||||
ret = c->status;
|
||||
if (p) {
|
||||
dma_addr_t addr = sa11x0_dma_pos(p);
|
||||
|
||||
dev_vdbg(d->slave.dev, "tx_status: addr:%x\n", addr);
|
||||
/*
|
||||
* If the cookie is on our issue queue, then the residue is
|
||||
* its total size.
|
||||
*/
|
||||
vd = vchan_find_desc(&c->vc, cookie);
|
||||
if (vd) {
|
||||
state->residue = container_of(vd, struct sa11x0_dma_desc, vd)->size;
|
||||
} else if (!p) {
|
||||
state->residue = 0;
|
||||
} else {
|
||||
struct sa11x0_dma_desc *txd;
|
||||
size_t bytes = 0;
|
||||
|
||||
txd = p->txd_done;
|
||||
if (p->txd_done && p->txd_done->vd.tx.cookie == cookie)
|
||||
txd = p->txd_done;
|
||||
else if (p->txd_load && p->txd_load->vd.tx.cookie == cookie)
|
||||
txd = p->txd_load;
|
||||
else
|
||||
txd = NULL;
|
||||
|
||||
ret = c->status;
|
||||
if (txd) {
|
||||
dma_addr_t addr = sa11x0_dma_pos(p);
|
||||
unsigned i;
|
||||
|
||||
dev_vdbg(d->slave.dev, "tx_status: addr:%x\n", addr);
|
||||
|
||||
for (i = 0; i < txd->sglen; i++) {
|
||||
dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x\n",
|
||||
i, txd->sg[i].addr, txd->sg[i].len);
|
||||
|
|
@ -459,18 +494,11 @@ static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan,
|
|||
bytes += txd->sg[i].len;
|
||||
}
|
||||
}
|
||||
if (txd != p->txd_load && p->txd_load)
|
||||
bytes += p->txd_load->size;
|
||||
}
|
||||
list_for_each_entry(txd, &c->vc.desc_issued, vd.node) {
|
||||
bytes += txd->size;
|
||||
state->residue = bytes;
|
||||
}
|
||||
spin_unlock_irqrestore(&c->vc.lock, flags);
|
||||
|
||||
if (state)
|
||||
state->residue = bytes;
|
||||
|
||||
dev_vdbg(d->slave.dev, "tx_status: bytes 0x%zx\n", bytes);
|
||||
dev_vdbg(d->slave.dev, "tx_status: bytes 0x%zx\n", state->residue);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -584,6 +612,65 @@ static struct dma_async_tx_descriptor *sa11x0_dma_prep_slave_sg(
|
|||
return vchan_tx_prep(&c->vc, &txd->vd, flags);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *sa11x0_dma_prep_dma_cyclic(
|
||||
struct dma_chan *chan, dma_addr_t addr, size_t size, size_t period,
|
||||
enum dma_transfer_direction dir, void *context)
|
||||
{
|
||||
struct sa11x0_dma_chan *c = to_sa11x0_dma_chan(chan);
|
||||
struct sa11x0_dma_desc *txd;
|
||||
unsigned i, j, k, sglen, sgperiod;
|
||||
|
||||
/* SA11x0 channels can only operate in their native direction */
|
||||
if (dir != (c->ddar & DDAR_RW ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV)) {
|
||||
dev_err(chan->device->dev, "vchan %p: bad DMA direction: DDAR:%08x dir:%u\n",
|
||||
&c->vc, c->ddar, dir);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
sgperiod = DIV_ROUND_UP(period, DMA_MAX_SIZE & ~DMA_ALIGN);
|
||||
sglen = size * sgperiod / period;
|
||||
|
||||
/* Do not allow zero-sized txds */
|
||||
if (sglen == 0)
|
||||
return NULL;
|
||||
|
||||
txd = kzalloc(sizeof(*txd) + sglen * sizeof(txd->sg[0]), GFP_ATOMIC);
|
||||
if (!txd) {
|
||||
dev_dbg(chan->device->dev, "vchan %p: kzalloc failed\n", &c->vc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
for (i = k = 0; i < size / period; i++) {
|
||||
size_t tlen, len = period;
|
||||
|
||||
for (j = 0; j < sgperiod; j++, k++) {
|
||||
tlen = len;
|
||||
|
||||
if (tlen > DMA_MAX_SIZE) {
|
||||
unsigned mult = DIV_ROUND_UP(tlen, DMA_MAX_SIZE & ~DMA_ALIGN);
|
||||
tlen = (tlen / mult) & ~DMA_ALIGN;
|
||||
}
|
||||
|
||||
txd->sg[k].addr = addr;
|
||||
txd->sg[k].len = tlen;
|
||||
addr += tlen;
|
||||
len -= tlen;
|
||||
}
|
||||
|
||||
WARN_ON(len != 0);
|
||||
}
|
||||
|
||||
WARN_ON(k != sglen);
|
||||
|
||||
txd->ddar = c->ddar;
|
||||
txd->size = size;
|
||||
txd->sglen = sglen;
|
||||
txd->cyclic = 1;
|
||||
txd->period = sgperiod;
|
||||
|
||||
return vchan_tx_prep(&c->vc, &txd->vd, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
}
|
||||
|
||||
static int sa11x0_dma_slave_config(struct sa11x0_dma_chan *c, struct dma_slave_config *cfg)
|
||||
{
|
||||
u32 ddar = c->ddar & ((0xf << 4) | DDAR_RW);
|
||||
|
|
@ -854,7 +941,9 @@ static int __devinit sa11x0_dma_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
|
||||
d->slave.device_prep_slave_sg = sa11x0_dma_prep_slave_sg;
|
||||
d->slave.device_prep_dma_cyclic = sa11x0_dma_prep_dma_cyclic;
|
||||
ret = sa11x0_dma_init_dmadev(&d->slave, &pdev->dev);
|
||||
if (ret) {
|
||||
dev_warn(d->slave.dev, "failed to register slave async device: %d\n",
|
||||
|
|
|
|||
|
|
@ -21,8 +21,9 @@
|
|||
#include <linux/dmaengine.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
struct pl08x_lli;
|
||||
struct pl08x_driver_data;
|
||||
struct pl08x_phy_chan;
|
||||
struct pl08x_txd;
|
||||
|
||||
/* Bitmasks for selecting AHB ports for DMA transfers */
|
||||
enum {
|
||||
|
|
@ -46,169 +47,28 @@ enum {
|
|||
* devices with static assignments
|
||||
* @muxval: a number usually used to poke into some mux regiser to
|
||||
* mux in the signal to this channel
|
||||
* @cctl_opt: default options for the channel control register
|
||||
* @cctl_memcpy: options for the channel control register for memcpy
|
||||
* *** not used for slave channels ***
|
||||
* @addr: source/target address in physical memory for this DMA channel,
|
||||
* can be the address of a FIFO register for burst requests for example.
|
||||
* This can be left undefined if the PrimeCell API is used for configuring
|
||||
* this.
|
||||
* @circular_buffer: whether the buffer passed in is circular and
|
||||
* shall simply be looped round round (like a record baby round
|
||||
* round round round)
|
||||
* @single: the device connected to this channel will request single DMA
|
||||
* transfers, not bursts. (Bursts are default.)
|
||||
* @periph_buses: the device connected to this channel is accessible via
|
||||
* these buses (use PL08X_AHB1 | PL08X_AHB2).
|
||||
*/
|
||||
struct pl08x_channel_data {
|
||||
char *bus_id;
|
||||
const char *bus_id;
|
||||
int min_signal;
|
||||
int max_signal;
|
||||
u32 muxval;
|
||||
u32 cctl;
|
||||
u32 cctl_memcpy;
|
||||
dma_addr_t addr;
|
||||
bool circular_buffer;
|
||||
bool single;
|
||||
u8 periph_buses;
|
||||
};
|
||||
|
||||
/**
|
||||
* Struct pl08x_bus_data - information of source or destination
|
||||
* busses for a transfer
|
||||
* @addr: current address
|
||||
* @maxwidth: the maximum width of a transfer on this bus
|
||||
* @buswidth: the width of this bus in bytes: 1, 2 or 4
|
||||
*/
|
||||
struct pl08x_bus_data {
|
||||
dma_addr_t addr;
|
||||
u8 maxwidth;
|
||||
u8 buswidth;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_phy_chan - holder for the physical channels
|
||||
* @id: physical index to this channel
|
||||
* @lock: a lock to use when altering an instance of this struct
|
||||
* @signal: the physical signal (aka channel) serving this physical channel
|
||||
* right now
|
||||
* @serving: the virtual channel currently being served by this physical
|
||||
* channel
|
||||
* @locked: channel unavailable for the system, e.g. dedicated to secure
|
||||
* world
|
||||
*/
|
||||
struct pl08x_phy_chan {
|
||||
unsigned int id;
|
||||
void __iomem *base;
|
||||
spinlock_t lock;
|
||||
int signal;
|
||||
struct pl08x_dma_chan *serving;
|
||||
bool locked;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_sg - structure containing data per sg
|
||||
* @src_addr: src address of sg
|
||||
* @dst_addr: dst address of sg
|
||||
* @len: transfer len in bytes
|
||||
* @node: node for txd's dsg_list
|
||||
*/
|
||||
struct pl08x_sg {
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
size_t len;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
|
||||
* @tx: async tx descriptor
|
||||
* @node: node for txd list for channels
|
||||
* @dsg_list: list of children sg's
|
||||
* @direction: direction of transfer
|
||||
* @llis_bus: DMA memory address (physical) start for the LLIs
|
||||
* @llis_va: virtual memory address start for the LLIs
|
||||
* @cctl: control reg values for current txd
|
||||
* @ccfg: config reg values for current txd
|
||||
*/
|
||||
struct pl08x_txd {
|
||||
struct dma_async_tx_descriptor tx;
|
||||
struct list_head node;
|
||||
struct list_head dsg_list;
|
||||
enum dma_transfer_direction direction;
|
||||
dma_addr_t llis_bus;
|
||||
struct pl08x_lli *llis_va;
|
||||
/* Default cctl value for LLIs */
|
||||
u32 cctl;
|
||||
/*
|
||||
* Settings to be put into the physical channel when we
|
||||
* trigger this txd. Other registers are in llis_va[0].
|
||||
*/
|
||||
u32 ccfg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
|
||||
* states
|
||||
* @PL08X_CHAN_IDLE: the channel is idle
|
||||
* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
|
||||
* channel and is running a transfer on it
|
||||
* @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
|
||||
* channel, but the transfer is currently paused
|
||||
* @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
|
||||
* channel to become available (only pertains to memcpy channels)
|
||||
*/
|
||||
enum pl08x_dma_chan_state {
|
||||
PL08X_CHAN_IDLE,
|
||||
PL08X_CHAN_RUNNING,
|
||||
PL08X_CHAN_PAUSED,
|
||||
PL08X_CHAN_WAITING,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
|
||||
* @chan: wrappped abstract channel
|
||||
* @phychan: the physical channel utilized by this channel, if there is one
|
||||
* @phychan_hold: if non-zero, hold on to the physical channel even if we
|
||||
* have no pending entries
|
||||
* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
|
||||
* @name: name of channel
|
||||
* @cd: channel platform data
|
||||
* @runtime_addr: address for RX/TX according to the runtime config
|
||||
* @runtime_direction: current direction of this channel according to
|
||||
* runtime config
|
||||
* @pend_list: queued transactions pending on this channel
|
||||
* @at: active transaction on this channel
|
||||
* @lock: a lock for this channel data
|
||||
* @host: a pointer to the host (internal use)
|
||||
* @state: whether the channel is idle, paused, running etc
|
||||
* @slave: whether this channel is a device (slave) or for memcpy
|
||||
* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
|
||||
* channels. Fill with 'true' if peripheral should be flow controller. Direction
|
||||
* will be selected at Runtime.
|
||||
* @waiting: a TX descriptor on this channel which is waiting for a physical
|
||||
* channel to become available
|
||||
*/
|
||||
struct pl08x_dma_chan {
|
||||
struct dma_chan chan;
|
||||
struct pl08x_phy_chan *phychan;
|
||||
int phychan_hold;
|
||||
struct tasklet_struct tasklet;
|
||||
char *name;
|
||||
const struct pl08x_channel_data *cd;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
u32 src_cctl;
|
||||
u32 dst_cctl;
|
||||
enum dma_transfer_direction runtime_direction;
|
||||
struct list_head pend_list;
|
||||
struct pl08x_txd *at;
|
||||
spinlock_t lock;
|
||||
struct pl08x_driver_data *host;
|
||||
enum pl08x_dma_chan_state state;
|
||||
bool slave;
|
||||
bool device_fc;
|
||||
struct pl08x_txd *waiting;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_platform_data - the platform configuration for the PL08x
|
||||
* PrimeCells.
|
||||
|
|
@ -229,8 +89,8 @@ struct pl08x_platform_data {
|
|||
const struct pl08x_channel_data *slave_channels;
|
||||
unsigned int num_slave_channels;
|
||||
struct pl08x_channel_data memcpy_channel;
|
||||
int (*get_signal)(struct pl08x_dma_chan *);
|
||||
void (*put_signal)(struct pl08x_dma_chan *);
|
||||
int (*get_signal)(const struct pl08x_channel_data *);
|
||||
void (*put_signal)(const struct pl08x_channel_data *, int);
|
||||
u8 lli_buses;
|
||||
u8 mem_buses;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue