From 743ac9d2216014927a8e58942ba96d4fb27685db Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 30 Apr 2015 15:30:00 +0200 Subject: [PATCH 01/17] ARM: DT: STi: STiH407: Update picophyreset for the usb3 controllers usb2 phy Ths picophyreset is incorrectly defined, which stops the usb2 phy being taken out of reset. Signed-off-by: Peter Griffin Acked-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 85159b823867..363db4b544c9 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -282,7 +282,7 @@ #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; + <&picophyreset STIH407_PICOPHY2_RESET>; reset-names = "global", "port"; }; From fd55599834d6bb3f6dd90a7aa0a87e4616461261 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 30 Apr 2015 15:30:00 +0200 Subject: [PATCH 02/17] ARM: DT: STi: STiH407: Add dwc3 usb3 DT node. Now that both usb2 and usb3 phy drivers, and also the ST dwc3 glue code are all present upstream, we can add the dwc3 DT node and have a working usb3 controller on stih407-b2120 and stih410-b2020. Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 363db4b544c9..bec7e82a0844 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -516,5 +516,32 @@ status = "disabled"; }; + + st_dwc3: dwc3@8f94000 { + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + ranges; + + status = "disabled"; + + dwc3: dwc3@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = ; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy0>, + <&phy_port2 PHY_TYPE_USB3>; + }; + }; }; }; From 571ac3be06f1b35b53994a2d45c3f0cf4c2a9959 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 30 Apr 2015 15:30:00 +0200 Subject: [PATCH 03/17] ARM: DT: STi: stihxxx-b2120: Enable USB3 port on stih407-b2120 and stih410-b2120 The USB3 controller is present on both variants of the b2120 board so enable the controller in the generic stihxxx-b2120.dtsi file. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stihxxx-b2120.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 64fa0b5a0f24..f589fe487f13 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -74,5 +74,10 @@ st,osc-force-ext; }; }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + }; }; From 0dee58e66f3ef68464c951d912e0b6215240fdad Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 30 Apr 2015 15:30:00 +0200 Subject: [PATCH 04/17] ARM: DT: STi: STiH418: Add miphy28lp optional oscillator clock properties STiH418 miphy28lp port0/1 need the oscillator clock configured in the same way as on STiH407/STiH410 platforms. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih418-b2199.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index a2fdada5b4e5..589f66b501c2 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -86,5 +86,16 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; }; }; From 5f636b75099fc09e31ce4d8b520bded06785edab Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Thu, 30 Apr 2015 15:30:00 +0200 Subject: [PATCH 05/17] ARM: DT: STi: STiH418: Enable USB3 port on stih418-b2199. The USB3 controller is present on the b2199 board, so enable it in the board specific DT file. Signed-off-by: Peter Griffin Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih418-b2199.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 589f66b501c2..82eee39ccb31 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -97,5 +97,9 @@ st,osc-force-ext; }; }; + + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; }; }; From 416ef034cbc5280aab16a64cbb1116c588cd02b4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 06/17] ARM: STi: STiH407: Add DT nodes for for PWM Supply top level nodes for the STiH407 based development boards. The Pinctrl configuration has already been applied, so the only missing piece of the DT puzzle is for a board's DTB to enable the nodes. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 3efa3b2ebe90..2c560fc30503 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -147,5 +147,33 @@ }; }; }; + + /* COMMS PWM Module */ + pwm0: pwm@9810000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + }; + + /* SBC PWM Module */ + pwm1: pwm@9510000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + }; }; }; From 9723bac00bb71475ff96e1b1252e5c5cff3e116b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 07/17] ARM: STi: STiH416: Add Pinctrl settings for PWM Supply the Pinctrl configuration to enable PWM{0,1} lines on STiH416 based development boards. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 50 ++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 9cccf2d6aa26..051fc16f3706 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -216,6 +216,29 @@ }; }; }; + + pwm1 { + pinctrl_pwm1_chan0_default: pwm1-0-default { + st,pins { + pwm-out = <&pio3 0 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan1_default: pwm1-1-default { + st,pins { + pwm-out = <&pio4 4 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan2_default: pwm1-2-default { + st,pins { + pwm-out = <&pio4 6 ALT3 OUT>; + }; + }; + pinctrl_pwm1_chan3_default: pwm1-3-default { + st,pins { + pwm-out = <&pio4 7 ALT3 OUT>; + }; + }; + }; }; pin-controller-front { @@ -310,6 +333,14 @@ st,bank-name = "PIO31"; }; + pwm0 { + pinctrl_pwm0_chan0_default: pwm0-0-default { + st,pins { + pwm-out = <&pio9 7 ALT2 OUT>; + }; + }; + }; + serial2-oe { pinctrl_serial2_oe: serial2-1 { st,pins { @@ -540,6 +571,25 @@ }; }; }; + + pwm0 { + pinctrl_pwm0_chan1_default: pwm0-1-default { + st,pins { + pwm-out = <&pio13 2 ALT2 OUT>; + }; + }; + pinctrl_pwm0_chan2_default: pwm0-2-default { + st,pins { + pwm-out = <&pio15 2 ALT4 OUT>; + }; + }; + pinctrl_pwm0_chan3_default: pwm0-3-default { + st,pins { + pwm-out = <&pio17 4 ALT1 OUT>; + }; + }; + }; + }; pin-controller-fvdp-fe { From c66b2969758061b8107764de9809c1a1c4fd100d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 08/17] ARM: STi: STiH416: Add DT nodes for PWM Supply top level nodes for the STiH416 based development boards. The Pinctrl configuration has already been applied, so the only missing piece of the DT puzzle is for a board's DTB to enable the nodes. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 44 +++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index eeb7afecbbe6..9ead8bbb17a1 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -104,7 +104,7 @@ interrupts = <0 210 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&clk_sysin>; + clocks = <&clk_sysin>; }; i2c@fed40000 { @@ -445,5 +445,47 @@ <&softreset STIH416_USB3_SOFTRESET>; reset-names = "power", "softreset"; }; + + /* SAS PWM Module */ + pwm0: pwm@fed10000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0xfed10000 0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default + &pinctrl_pwm0_chan1_default + &pinctrl_pwm0_chan2_default + &pinctrl_pwm0_chan3_default>; + + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <4>; + }; + + /* SBC PWM Module */ + pwm1: pwm@fe510000 { + compatible = "st,sti-pwm"; + status = "disabled"; + #pwm-cells = <2>; + reg = <0xfe510000 0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + /* + * Shared with SBC_OBS_NOTRST. Don't + * enable unless you really know what + * you're doing. + * + * &pinctrl_pwm1_chan1_default + */ + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + + clock-names = "pwm"; + clocks = <&clk_sysin>; + st,pwm-num-chan = <3>; + }; }; }; From bc7dbcd08e6e450e37e1caa1e86f7205c6f32016 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 09/17] ARM: STi: STiH416-b2020e: Enable PWM on the B2020 Rev-E All the infrastructure is now in place for ST's PWM controller. This patch takes the final step and enables the IP on the 2020 Rev-E development platform. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416-b2020e.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts index 961799e1dc51..f1ceee192a0e 100644 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ b/arch/arm/boot/dts/stih416-b2020e.dts @@ -51,5 +51,15 @@ sata0: sata@fe380000{ status = "okay"; }; + + /* SAS PWM Module */ + pwm0: pwm@fed10000 { + status = "okay"; + }; + + /* SBC PWM Module */ + pwm1: pwm@fe510000 { + status = "okay"; + }; }; }; From 48f3fe6b1ee26e44781974aacba96b4eba003b73 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 10/17] ARM: STi: STiH407: Add Restart support for STiH407 Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index bec7e82a0844..710d2beb0966 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -65,6 +65,12 @@ ranges; compatible = "simple-bus"; + restart { + compatible = "st,stih407-restart"; + st,syscfg = <&syscfg_sbc_reg>; + status = "okay"; + }; + powerdown: powerdown-controller { compatible = "st,stih407-powerdown"; #reset-cells = <1>; From fb54eb10afd646177ffcab6e86ef0e56e48cae86 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 11/17] ARM: STi: STiH416: Add Restart support for STiH416 Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 9ead8bbb17a1..6452d3315200 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -30,6 +30,12 @@ ranges; compatible = "simple-bus"; + restart { + compatible = "st,stih416-restart"; + st,syscfg = <&syscfg_sbc>; + status = "okay"; + }; + powerdown: powerdown-controller { #reset-cells = <1>; compatible = "st,stih416-powerdown"; From c2808eeb28b1a732cd2f5805af2406c8f1c38740 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 12/17] ARM: STi: STiH416: Enable Cortex-A9 PMU support This is ARM's generic Performance Monitoring Unit. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 6452d3315200..cc5b78d51fa4 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -23,6 +23,12 @@ cache-level = <2>; }; + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = ; + }; + soc { #address-cells = <1>; #size-cells = <1>; From 3c7dd7ce4898c6f0e2c3de9add93ddf96cd32cbe Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 13/17] ARM: STi: STiH416: Enable PMU IRQs This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Here we are enabling PMU IRQs on both channels. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih416.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index cc5b78d51fa4..9dca173e694a 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -98,6 +99,15 @@ reg = <0xfe4b5100 0x8>; }; + irq-syscfg { + compatible = "st,stih416-irq-syscfg"; + st,syscfg = <&syscfg_cpu>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + serial2: serial@fed32000{ compatible = "st,asc"; status = "disabled"; From 00133b915396a1d2f321a3266198b2e56fa801fc Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 14/17] ARM: STi: STiH407: Enable Cortex-A9 PMU support This is ARM's generic Performance Monitoring Unit. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 710d2beb0966..e46774900b33 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -58,6 +58,12 @@ cache-level = <2>; }; + arm-pmu { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + soc { #address-cells = <1>; #size-cells = <1>; From 107dea0c2b393bc5b45f23ddb2b154f38489f46c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 15/17] ARM: STi: STiH407: Enable PMU IRQs This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Here we are enabling PMU IRQs on both channels. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index e46774900b33..838b812cbda1 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -127,6 +128,15 @@ reg = <0x94b5100 0x1000>; }; + irq-syscfg { + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; From 56439ab0e3ba2e62fe824f879ebea980f6a0e072 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 12 May 2015 14:51:00 +0200 Subject: [PATCH 16/17] ARM: STi: Ensure requested STi's SysCfg Controlled IRQs are enabled at boot This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/mach-sti/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index 3b1ac463a494..125865daaf17 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -1,6 +1,7 @@ menuconfig ARCH_STI bool "STMicroelectronics Consumer Electronics SOCs" if ARCH_MULTI_V7 select ARM_GIC + select ST_IRQCHIP select ARM_GLOBAL_TIMER select PINCTRL select PINCTRL_ST From 2cdce7a98b1fbd3839aec5fc79a0f237c9b75dcc Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 11 May 2015 16:12:00 +0200 Subject: [PATCH 17/17] ARM: STi: DT: STih407: Re-order #include <*.dtsi> files This patch fixes a regression where serial is enabled by the first (board) DTSI, then disabled by the second (SoC) file. To enable serial and keep it enabled, we need to include the file which enables it last. Reported-by: LAVA [via Peter Griffin ] Signed-off-by: Lee Jones Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-b2120.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index af487145cd89..6d93475be554 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -7,8 +7,8 @@ * published by the Free Software Foundation. */ /dts-v1/; -#include "stihxxx-b2120.dtsi" #include "stih407.dtsi" +#include "stihxxx-b2120.dtsi" / { model = "STiH407 B2120"; compatible = "st,stih407-b2120", "st,stih407";