redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

[PATCH] x86_64: On Intel systems when CPU has C3 don't use TSC 

On Intel systems generally the TSC stops in C3 or deeper,
so don't use it there. Follows similar logic on i386.

This should fix problems on Meroms.

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
hifive-unleashed-5.1
Andi Kleen 2006-07-29 21:42:37 +02:00 committed by Linus Torvalds
parent 260f659b23
commit 0e5f61b00c
1 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/x86_64/kernel/time.c
View File

@ -28,6 +28,7 @@
#include <linux/acpi.h>
#ifdef CONFIG_ACPI
#include <acpi/achware.h> /* for PM timer frequency */
#include <acpi/acpi_bus.h>
#endif
#include <asm/8253pit.h>
#include <asm/pgtable.h>
@ -953,11 +954,18 @@ __cpuinit int unsynchronized_tsc(void)
#ifdef CONFIG_SMP
if (apic_is_clustered_box())
return 1;
/* Intel systems are normally all synchronized. Exceptions
are handled in the check above. */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
return 0;
#endif
/* Most intel systems have synchronized TSCs except for
multi node systems */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
#ifdef CONFIG_ACPI
/* But TSC doesn't tick in C3 so don't use it there */
if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100)
return 1;
#endif
return 0;
}
/* Assume multi socket systems are not synchronized */
return num_present_cpus() > 1;
}