arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -287,6 +287,14 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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emac_rgmii_pins: emac0 {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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"PD12", "PD13", "PD15", "PD16", "PD17";
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function = "emac";
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drive-strength = <40>;
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};
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i2c0_pins: i2c0 {
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pins = "PA11", "PA12";
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function = "i2c0";
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@ -383,6 +391,32 @@
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clocks = <&osc24M>;
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};
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emac: ethernet@1c30000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c30000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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int_mii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&ccu CLK_BUS_EPHY>;
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resets = <&ccu RST_BUS_EPHY>;
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};
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};
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};
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spi0: spi@01c68000 {
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compatible = "allwinner,sun8i-h3-spi";
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reg = <0x01c68000 0x1000>;
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