ARM: mach-shmobile: Use CMT2 for timer on sh7372
Switch the sh7372 CPU support to use CMT2 instead of CMT1 for system timer. CMT1 is located in the A3SP power domain while CMT2 is located in the always-on power domain C5. This improves our PM situation - with CMT2 as timer we can power down A3SP and still access the timer. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -511,8 +511,8 @@ enum { MSTP001,
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MSTP223,
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MSTP218, MSTP217, MSTP216,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
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MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
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MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
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MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, MSTP400,
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MSTP_NR };
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#define MSTP(_parent, _reg, _bit, _flags) \
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@ -545,7 +545,6 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
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[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
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@ -559,6 +558,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
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[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
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[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
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[MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
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};
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#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
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@ -640,7 +640,6 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
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CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
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CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
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@ -658,6 +657,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
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CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
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CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
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CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
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@ -169,35 +169,35 @@ static struct platform_device scif6_device = {
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};
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/* CMT */
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.channel_offset = 0x10,
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.timer_bit = 0,
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static struct sh_timer_config cmt2_platform_data = {
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.name = "CMT2",
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.channel_offset = 0x40,
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.timer_bit = 5,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt10_resources[] = {
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static struct resource cmt2_resources[] = {
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[0] = {
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.name = "CMT10",
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.start = 0xe6138010,
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.end = 0xe613801b,
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.name = "CMT2",
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.start = 0xe6130040,
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.end = 0xe613004b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x0b00), /* CMT1_CMT10 */
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.start = evt2irq(0x0b80), /* CMT2 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt10_device = {
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static struct platform_device cmt2_device = {
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.name = "sh_cmt",
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.id = 10,
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.id = 2,
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.dev = {
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.platform_data = &cmt10_platform_data,
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.platform_data = &cmt2_platform_data,
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},
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.resource = cmt10_resources,
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.num_resources = ARRAY_SIZE(cmt10_resources),
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.resource = cmt2_resources,
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.num_resources = ARRAY_SIZE(cmt2_resources),
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};
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/* TMU */
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@ -818,7 +818,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
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&scif4_device,
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&scif5_device,
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&scif6_device,
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&cmt10_device,
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&cmt2_device,
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&tmu00_device,
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&tmu01_device,
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};
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