x86: cpu/common.c more cleanups
Complete/fix the cleanups of cpu/common.c: - fix ugly warning due to asm/topology.h -> linux/topology.h change - standardize the style across the file - simplify/refactor the code flow where possible Cc: Jaswinder Singh Rajput <jaswinder@kernel.org> LKML-Reference: <1237009789.4387.2.camel@localhost.localdomain> Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Ingo Molnar
parent
9766cdbcb2
commit
0f3fa48a7e
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@ -1,4 +1,3 @@
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#include <linux/topology.h>
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#include <linux/bootmem.h>
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#include <linux/linkage.h>
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#include <linux/bitops.h>
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@ -18,6 +17,7 @@
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#include <asm/hypervisor.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/topology.h>
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#include <asm/cpumask.h>
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#include <asm/pgtable.h>
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#include <asm/atomic.h>
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@ -82,45 +82,45 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
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* TLS descriptors are currently at a different place compared to i386.
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* Hopefully nobody expects them at a fixed place (Wine?)
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*/
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[GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
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[GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
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[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
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[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
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[GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
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[GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
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[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
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[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
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#else
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
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[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
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[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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/*
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* Segments used for calling PnP BIOS have byte granularity.
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* They code segments and data segments have fixed 64k limits,
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* the transfer segment sizes are set at run time.
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*/
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/* 32-bit code */
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[GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
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[GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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[GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
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[GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
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[GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
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[GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
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/* 16-bit data */
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[GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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[GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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/*
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* The APM segments have byte granularity and their bases
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* are set at run time. All have 64k limits.
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*/
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/* 32-bit code */
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[GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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[GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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/* 16-bit code */
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[GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
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[GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
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/* data */
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[GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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[GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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[GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
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[GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
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[GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
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[GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
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GDT_STACK_CANARY_INIT
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#endif
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} };
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@ -164,16 +164,17 @@ static inline int flag_is_changeable_p(u32 flag)
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* the CPUID. Add "volatile" to not allow gcc to
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* optimize the subsequent calls to this function.
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*/
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asm volatile ("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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asm volatile ("pushfl \n\t"
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"pushfl \n\t"
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"popl %0 \n\t"
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"movl %0, %1 \n\t"
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"xorl %2, %0 \n\t"
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"pushl %0 \n\t"
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"popfl \n\t"
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"pushfl \n\t"
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"popl %0 \n\t"
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"popfl \n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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@ -188,18 +189,22 @@ static int __cpuinit have_cpuid_p(void)
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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/* Disable processor serial number */
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unsigned long lo, hi;
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_cpu_cap(c, X86_FEATURE_PN);
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unsigned long lo, hi;
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
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return;
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/* Disable processor serial number: */
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_cpu_cap(c, X86_FEATURE_PN);
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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static int __init x86_serial_nr_setup(char *s)
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@ -232,6 +237,7 @@ struct cpuid_dependent_feature {
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u32 feature;
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u32 level;
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};
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static const struct cpuid_dependent_feature __cpuinitconst
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cpuid_dependent_features[] = {
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{ X86_FEATURE_MWAIT, 0x00000005 },
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@ -245,6 +251,9 @@ static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
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const struct cpuid_dependent_feature *df;
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for (df = cpuid_dependent_features; df->feature; df++) {
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if (!cpu_has(c, df->feature))
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continue;
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/*
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* Note: cpuid_level is set to -1 if unavailable, but
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* extended_extended_level is set to 0 if unavailable
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@ -252,26 +261,26 @@ static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
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* when signed; hence the weird messing around with
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* signs here...
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*/
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if (cpu_has(c, df->feature) &&
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((s32)df->level < 0 ?
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if (!((s32)df->level < 0 ?
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(u32)df->level > (u32)c->extended_cpuid_level :
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(s32)df->level > (s32)c->cpuid_level)) {
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clear_cpu_cap(c, df->feature);
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if (warn)
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printk(KERN_WARNING
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"CPU: CPU feature %s disabled "
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"due to lack of CPUID level 0x%x\n",
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x86_cap_flags[df->feature],
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df->level);
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}
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(s32)df->level > (s32)c->cpuid_level))
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continue;
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clear_cpu_cap(c, df->feature);
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if (!warn)
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continue;
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printk(KERN_WARNING
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"CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
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x86_cap_flags[df->feature], df->level);
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}
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}
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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*
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* in particular, if CPUID levels 0x80000002..4 are supported, this
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* isn't used
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*/
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/* Look up CPU names by table lookup. */
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@ -308,8 +317,10 @@ void load_percpu_segment(int cpu)
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load_stack_canary_segment();
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}
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/* Current gdt points %fs at the "master" per-cpu area: after this,
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* it's on the real one. */
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/*
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* Current gdt points %fs at the "master" per-cpu area: after this,
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* it's on the real one.
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*/
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void switch_to_new_gdt(int cpu)
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{
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struct desc_ptr gdt_descr;
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@ -355,14 +366,16 @@ static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
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if (c->extended_cpuid_level < 0x80000004)
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return;
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v = (unsigned int *) c->x86_model_id;
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v = (unsigned int *)c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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/* Intel chips right-justify this string for some dumb reason;
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undo that brain damage */
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/*
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* Intel chips right-justify this string for some dumb reason;
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* undo that brain damage:
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*/
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p = q = &c->x86_model_id[0];
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while (*p == ' ')
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p++;
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@ -439,29 +452,31 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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if (smp_num_siblings == 1) {
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printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
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} else if (smp_num_siblings > 1) {
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if (smp_num_siblings > nr_cpu_ids) {
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pr_warning("CPU: Unsupported number of siblings %d",
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smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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index_msb = get_count_order(smp_num_siblings);
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c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid,
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index_msb);
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smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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index_msb = get_count_order(smp_num_siblings);
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core_bits = get_count_order(c->x86_max_cores);
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c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
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((1 << core_bits) - 1);
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goto out;
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}
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if (smp_num_siblings <= 1)
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goto out;
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if (smp_num_siblings > nr_cpu_ids) {
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pr_warning("CPU: Unsupported number of siblings %d",
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smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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index_msb = get_count_order(smp_num_siblings);
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c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
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smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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index_msb = get_count_order(smp_num_siblings);
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core_bits = get_count_order(c->x86_max_cores);
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c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
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((1 << core_bits) - 1);
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out:
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if ((c->x86_max_cores * smp_num_siblings) > 1) {
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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@ -475,8 +490,8 @@ out:
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static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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{
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char *v = c->x86_vendor_id;
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int i;
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static int printed;
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int i;
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for (i = 0; i < X86_VENDOR_NUM; i++) {
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if (!cpu_devs[i])
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@ -485,6 +500,7 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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this_cpu = cpu_devs[i];
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c->x86_vendor = this_cpu->c_x86_vendor;
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return;
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@ -493,8 +509,9 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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if (!printed) {
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printed++;
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printk(KERN_ERR "CPU: vendor_id '%s'"
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"unknown, using generic init.\n", v);
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printk(KERN_ERR
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"CPU: vendor_id '%s' unknown, using generic init.\n", v);
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printk(KERN_ERR "CPU: Your system may be unstable.\n");
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}
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@ -514,14 +531,17 @@ void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xf) << 4;
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if (cap0 & (1<<19)) {
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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c->x86_cache_alignment = c->x86_clflush_size;
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@ -537,6 +557,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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@ -545,6 +566,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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c->extended_cpuid_level = xlvl;
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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@ -762,8 +784,8 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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squash_the_stupid_serial_number(c);
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/*
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* The vendor-specific functions might have changed features. Now
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* we do "generic changes."
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* The vendor-specific functions might have changed features.
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* Now we do "generic changes."
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*/
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/* Filter out anything that depends on CPUID levels we don't have */
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@ -846,8 +868,8 @@ void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
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}
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struct msr_range {
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unsigned min;
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unsigned max;
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unsigned min;
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unsigned max;
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};
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static struct msr_range msr_range_array[] __cpuinitdata = {
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@ -859,14 +881,15 @@ static struct msr_range msr_range_array[] __cpuinitdata = {
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static void __cpuinit print_cpu_msr(void)
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{
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unsigned index_min, index_max;
|
||||
unsigned index;
|
||||
u64 val;
|
||||
int i;
|
||||
unsigned index_min, index_max;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
|
||||
index_min = msr_range_array[i].min;
|
||||
index_max = msr_range_array[i].max;
|
||||
|
||||
for (index = index_min; index < index_max; index++) {
|
||||
if (rdmsrl_amd_safe(index, &val))
|
||||
continue;
|
||||
|
|
@ -876,6 +899,7 @@ static void __cpuinit print_cpu_msr(void)
|
|||
}
|
||||
|
||||
static int show_msr __cpuinitdata;
|
||||
|
||||
static __init int setup_show_msr(char *arg)
|
||||
{
|
||||
int num;
|
||||
|
|
@ -899,10 +923,12 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|||
{
|
||||
char *vendor = NULL;
|
||||
|
||||
if (c->x86_vendor < X86_VENDOR_NUM)
|
||||
if (c->x86_vendor < X86_VENDOR_NUM) {
|
||||
vendor = this_cpu->c_vendor;
|
||||
else if (c->cpuid_level >= 0)
|
||||
vendor = c->x86_vendor_id;
|
||||
} else {
|
||||
if (c->cpuid_level >= 0)
|
||||
vendor = c->x86_vendor_id;
|
||||
}
|
||||
|
||||
if (vendor && !strstr(c->x86_model_id, vendor))
|
||||
printk(KERN_CONT "%s ", vendor);
|
||||
|
|
@ -929,10 +955,12 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
|
|||
static __init int setup_disablecpuid(char *arg)
|
||||
{
|
||||
int bit;
|
||||
|
||||
if (get_option(&arg, &bit) && bit < NCAPINTS*32)
|
||||
setup_clear_cpu_cap(bit);
|
||||
else
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
__setup("clearcpuid=", setup_disablecpuid);
|
||||
|
|
@ -942,6 +970,7 @@ struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
|
|||
|
||||
DEFINE_PER_CPU_FIRST(union irq_stack_union,
|
||||
irq_stack_union) __aligned(PAGE_SIZE);
|
||||
|
||||
DEFINE_PER_CPU(char *, irq_stack_ptr) =
|
||||
init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
|
||||
|
||||
|
|
@ -951,6 +980,17 @@ EXPORT_PER_CPU_SYMBOL(kernel_stack);
|
|||
|
||||
DEFINE_PER_CPU(unsigned int, irq_count) = -1;
|
||||
|
||||
/*
|
||||
* Special IST stacks which the CPU switches to when it calls
|
||||
* an IST-marked descriptor entry. Up to 7 stacks (hardware
|
||||
* limit), all of them are 4K, except the debug stack which
|
||||
* is 8K.
|
||||
*/
|
||||
static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
|
||||
[0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
|
||||
[DEBUG_STACK - 1] = DEBUG_STKSZ
|
||||
};
|
||||
|
||||
static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
|
||||
[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
|
||||
__aligned(PAGE_SIZE);
|
||||
|
|
@ -984,7 +1024,7 @@ unsigned long kernel_eflags;
|
|||
*/
|
||||
DEFINE_PER_CPU(struct orig_ist, orig_ist);
|
||||
|
||||
#else /* x86_64 */
|
||||
#else /* CONFIG_X86_64 */
|
||||
|
||||
#ifdef CONFIG_CC_STACKPROTECTOR
|
||||
DEFINE_PER_CPU(unsigned long, stack_canary);
|
||||
|
|
@ -996,9 +1036,10 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
|
|||
memset(regs, 0, sizeof(struct pt_regs));
|
||||
regs->fs = __KERNEL_PERCPU;
|
||||
regs->gs = __KERNEL_STACK_CANARY;
|
||||
|
||||
return regs;
|
||||
}
|
||||
#endif /* x86_64 */
|
||||
#endif /* CONFIG_X86_64 */
|
||||
|
||||
/*
|
||||
* Clear all 6 debug registers:
|
||||
|
|
@ -1024,15 +1065,20 @@ static void clear_all_debug_regs(void)
|
|||
* A lot of state is already set up in PDA init for 64 bit
|
||||
*/
|
||||
#ifdef CONFIG_X86_64
|
||||
|
||||
void __cpuinit cpu_init(void)
|
||||
{
|
||||
int cpu = stack_smp_processor_id();
|
||||
struct tss_struct *t = &per_cpu(init_tss, cpu);
|
||||
struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
|
||||
unsigned long v;
|
||||
struct orig_ist *orig_ist;
|
||||
struct task_struct *me;
|
||||
struct tss_struct *t;
|
||||
unsigned long v;
|
||||
int cpu;
|
||||
int i;
|
||||
|
||||
cpu = stack_smp_processor_id();
|
||||
t = &per_cpu(init_tss, cpu);
|
||||
orig_ist = &per_cpu(orig_ist, cpu);
|
||||
|
||||
#ifdef CONFIG_NUMA
|
||||
if (cpu != 0 && percpu_read(node_number) == 0 &&
|
||||
cpu_to_node(cpu) != NUMA_NO_NODE)
|
||||
|
|
@ -1073,19 +1119,17 @@ void __cpuinit cpu_init(void)
|
|||
* set up and load the per-CPU TSS
|
||||
*/
|
||||
if (!orig_ist->ist[0]) {
|
||||
static const unsigned int sizes[N_EXCEPTION_STACKS] = {
|
||||
[0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
|
||||
[DEBUG_STACK - 1] = DEBUG_STKSZ
|
||||
};
|
||||
char *estacks = per_cpu(exception_stacks, cpu);
|
||||
|
||||
for (v = 0; v < N_EXCEPTION_STACKS; v++) {
|
||||
estacks += sizes[v];
|
||||
estacks += exception_stack_sizes[v];
|
||||
orig_ist->ist[v] = t->x86_tss.ist[v] =
|
||||
(unsigned long)estacks;
|
||||
}
|
||||
}
|
||||
|
||||
t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
|
||||
|
||||
/*
|
||||
* <= is required because the CPU will access up to
|
||||
* 8 bits beyond the end of the IO permission bitmap.
|
||||
|
|
@ -1187,5 +1231,4 @@ void __cpuinit cpu_init(void)
|
|||
|
||||
xsave_init();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue