myri10ge: update firmware headers
Update myri10ge firmware headers. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Andrew Gallatin <gallatin@myri.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>hifive-unleashed-5.1
Brice Goglin
Jeff Garzik
parent
e8f720fdec
commit
0f7229dde3
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@ -10,7 +10,7 @@ struct mcp_dma_addr {
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__be32 low;
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};
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/* 4 Bytes. 8 Bytes for NDIS drivers. */
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/* 4 Bytes */
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struct mcp_slot {
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__sum16 checksum;
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__be16 length;
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@ -144,6 +144,7 @@ enum myri10ge_mcp_cmd_type {
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* a power of 2 number of entries. */
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MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
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#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
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/* command to bring ethernet interface up. Above parameters
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* (plus mtu & mac address) must have been exchanged prior
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@ -221,10 +222,14 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_GET_MAX_RSS_QUEUES,
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MXGEFW_CMD_ENABLE_RSS_QUEUES,
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/* data0 = number of slices n (0, 1, ..., n-1) to enable
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* data1 = interrupt mode. 0=share one INTx/MSI, 1=use one MSI-X per queue.
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* data1 = interrupt mode.
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* 0=share one INTx/MSI, 1=use one MSI-X per queue.
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* If all queues share one interrupt, the driver must have set
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* RSS_SHARED_INTERRUPT_DMA before enabling queues.
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*/
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#define MXGEFW_SLICE_INTR_MODE_SHARED 0
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#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1
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MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
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MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
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/* data0, data1 = bus address lsw, msw */
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@ -241,10 +246,14 @@ enum myri10ge_mcp_cmd_type {
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* 0: disable rss. nic does not distribute receive packets.
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* 1: enable rss. nic distributes receive packets among queues.
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* data1 = hash type
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* 1: IPV4
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* 2: TCP_IPV4
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* 3: IPV4 | TCP_IPV4
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* 1: IPV4 (required by RSS)
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* 2: TCP_IPV4 (required by RSS)
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* 3: IPV4 | TCP_IPV4 (required by RSS)
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* 4: source port
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*/
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#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1
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#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2
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#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4
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MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
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/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
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@ -260,6 +269,8 @@ enum myri10ge_mcp_cmd_type {
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* 0: Linux/FreeBSD style (NIC default)
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* 1: NDIS/NetBSD style
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*/
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#define MXGEFW_TSO_MODE_LINUX 0
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#define MXGEFW_TSO_MODE_NDIS 1
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MXGEFW_CMD_MDIO_READ,
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/* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
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@ -286,6 +297,38 @@ enum myri10ge_mcp_cmd_type {
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/* Return data = NIC memory offset of mcp_vpump_public_global */
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MXGEFW_CMD_RESET_VPUMP,
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/* Resets the VPUMP state */
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MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE,
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/* data0 = mcp_slot type to use.
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* 0 = the default 4B mcp_slot
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* 1 = 8B mcp_slot_8
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*/
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#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
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#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1
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MXGEFW_CMD_SET_THROTTLE_FACTOR,
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/* set the throttle factor for ethp_z8e
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* data0 = throttle_factor
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* throttle_factor = 256 * pcie-raw-speed / tx_speed
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* tx_speed = 256 * pcie-raw-speed / throttle_factor
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*
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* For PCI-E x8: pcie-raw-speed == 16Gb/s
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* For PCI-E x4: pcie-raw-speed == 8Gb/s
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*
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* ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
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* ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
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*
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* with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
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* with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
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*/
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MXGEFW_CMD_VPUMP_UP,
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/* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
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MXGEFW_CMD_GET_VPUMP_CLK,
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/* Get the lanai clock */
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MXGEFW_CMD_GET_DCA_OFFSET,
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/* offset of dca control for WDMAs */
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};
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enum myri10ge_mcp_cmd_status {
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@ -302,7 +345,8 @@ enum myri10ge_mcp_cmd_status {
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MXGEFW_CMD_ERROR_UNALIGNED,
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MXGEFW_CMD_ERROR_NO_MDIO,
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MXGEFW_CMD_ERROR_XFP_FAILURE,
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MXGEFW_CMD_ERROR_XFP_ABSENT
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MXGEFW_CMD_ERROR_XFP_ABSENT,
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MXGEFW_CMD_ERROR_BAD_PCIE_LINK
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};
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#define MXGEFW_OLD_IRQ_DATA_LEN 40
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@ -1,30 +1,6 @@
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#ifndef __MYRI10GE_MCP_GEN_HEADER_H__
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#define __MYRI10GE_MCP_GEN_HEADER_H__
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/* this file define a standard header used as a first entry point to
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* exchange information between firmware/driver and driver. The
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* header structure can be anywhere in the mcp. It will usually be in
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* the .data section, because some fields needs to be initialized at
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* compile time.
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* The 32bit word at offset MX_HEADER_PTR_OFFSET in the mcp must
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* contains the location of the header.
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*
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* Typically a MCP will start with the following:
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* .text
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* .space 52 ! to help catch MEMORY_INT errors
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* bt start ! jump to real code
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* nop
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* .long _gen_mcp_header
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*
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* The source will have a definition like:
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*
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* mcp_gen_header_t gen_mcp_header = {
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* .header_length = sizeof(mcp_gen_header_t),
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* .mcp_type = MCP_TYPE_XXX,
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* .version = "something $Id: mcp_gen_header.h,v 1.2 2006/05/13 10:04:35 bgoglin Exp $",
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* .mcp_globals = (unsigned)&Globals
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* };
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*/
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#define MCP_HEADER_PTR_OFFSET 0x3c
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@ -32,13 +8,14 @@
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#define MCP_TYPE_PCIE 0x70636965 /* "PCIE" pcie-only MCP */
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#define MCP_TYPE_ETH 0x45544820 /* "ETH " */
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#define MCP_TYPE_MCP0 0x4d435030 /* "MCP0" */
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#define MCP_TYPE_DFLT 0x20202020 /* " " */
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struct mcp_gen_header {
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/* the first 4 fields are filled at compile time */
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unsigned header_length;
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__be32 mcp_type;
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char version[128];
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unsigned mcp_globals; /* pointer to mcp-type specific structure */
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unsigned mcp_private; /* pointer to mcp-type specific structure */
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/* filled by the MCP at run-time */
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unsigned sram_size;
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@ -53,6 +30,18 @@ struct mcp_gen_header {
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*
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* Never remove any field. Keep everything naturally align.
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*/
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/* Specifies if the running mcp is mcp0, 1, or 2. */
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unsigned char mcp_index;
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unsigned char disable_rabbit;
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unsigned char unaligned_tlp;
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unsigned char pad1;
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unsigned counters_addr;
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unsigned copy_block_info; /* for small mcps loaded with "lload -d" */
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unsigned short handoff_id_major; /* must be equal */
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unsigned short handoff_id_caps; /* bitfield: new mcp must have superset */
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unsigned msix_table_addr; /* start address of msix table in firmware */
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/* 8 */
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};
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#endif /* __MYRI10GE_MCP_GEN_HEADER_H__ */
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