drm/radeon/kms/evergreen: add gart support
Gart setup is more or less like r7xx. Copy rv770d.h to evergreend.h and fix up changes. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
49f6598277
commit
0fcdb61e78
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@ -27,7 +27,7 @@
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_drm.h"
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#include "rv770d.h"
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#include "evergreend.h"
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#include "atom.h"
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#include "avivod.h"
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#include "evergreen_reg.h"
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@ -82,10 +82,31 @@ static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
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/*
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* GART
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*/
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void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
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{
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unsigned i;
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u32 tmp;
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WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
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tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
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if (tmp == 2) {
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printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
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return;
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}
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if (tmp) {
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return;
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}
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udelay(1);
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}
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}
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int evergreen_pcie_gart_enable(struct radeon_device *rdev)
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{
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u32 tmp;
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int r, i;
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int r;
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if (rdev->gart.table.vram.robj == NULL) {
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dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
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@ -120,10 +141,9 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
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WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
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(u32)(rdev->dummy_page.addr >> 12));
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for (i = 1; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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WREG32(VM_CONTEXT1_CNTL, 0);
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r600_pcie_gart_tlb_flush(rdev);
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evergreen_pcie_gart_tlb_flush(rdev);
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rdev->gart.ready = true;
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return 0;
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}
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@ -131,11 +151,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
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void evergreen_pcie_gart_disable(struct radeon_device *rdev)
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{
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u32 tmp;
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int i, r;
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int r;
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/* Disable all tables */
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for (i = 0; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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WREG32(VM_CONTEXT0_CNTL, 0);
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WREG32(VM_CONTEXT1_CNTL, 0);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
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@ -172,7 +192,6 @@ void evergreen_pcie_gart_fini(struct radeon_device *rdev)
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void evergreen_agp_enable(struct radeon_device *rdev)
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{
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u32 tmp;
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int i;
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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@ -192,8 +211,8 @@ void evergreen_agp_enable(struct radeon_device *rdev)
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WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
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WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
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for (i = 0; i < 7; i++)
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WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
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WREG32(VM_CONTEXT0_CNTL, 0);
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WREG32(VM_CONTEXT1_CNTL, 0);
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}
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static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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@ -500,9 +519,9 @@ int evergreen_asic_reset(struct radeon_device *rdev)
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static int evergreen_startup(struct radeon_device *rdev)
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{
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#if 0
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int r;
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#if 0
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if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
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r = r600_init_microcode(rdev);
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if (r) {
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@ -512,15 +531,13 @@ static int evergreen_startup(struct radeon_device *rdev)
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}
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#endif
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evergreen_mc_program(rdev);
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#if 0
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if (rdev->flags & RADEON_IS_AGP) {
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evergreem_agp_enable(rdev);
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evergreen_agp_enable(rdev);
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} else {
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r = evergreen_pcie_gart_enable(rdev);
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if (r)
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return r;
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}
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#endif
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evergreen_gpu_init(rdev);
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#if 0
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if (!rdev->r600_blit.shader_obj) {
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@ -607,7 +624,10 @@ int evergreen_suspend(struct radeon_device *rdev)
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r700_cp_stop(rdev);
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rdev->cp.ready = false;
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r600_wb_disable(rdev);
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#endif
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evergreen_pcie_gart_disable(rdev);
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#if 0
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/* unpin shaders bo */
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r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
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if (likely(r == 0)) {
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@ -717,18 +737,18 @@ int evergreen_init(struct radeon_device *rdev)
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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#endif
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r = r600_pcie_gart_init(rdev);
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if (r)
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return r;
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#endif
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rdev->accel_working = false;
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r = evergreen_startup(rdev);
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if (r) {
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evergreen_suspend(rdev);
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/*r600_wb_fini(rdev);*/
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/*radeon_ring_fini(rdev);*/
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/*evergreen_pcie_gart_fini(rdev);*/
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evergreen_pcie_gart_fini(rdev);
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rdev->accel_working = false;
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}
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if (rdev->accel_working) {
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@ -756,8 +776,8 @@ void evergreen_fini(struct radeon_device *rdev)
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radeon_irq_kms_fini(rdev);
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radeon_ring_fini(rdev);
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r600_wb_fini(rdev);
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evergreen_pcie_gart_fini(rdev);
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#endif
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evergreen_pcie_gart_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_clocks_fini(rdev);
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270
drivers/gpu/drm/radeon/evergreend.h
Normal file
270
drivers/gpu/drm/radeon/evergreend.h
Normal file
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@ -0,0 +1,270 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef EVERGREEND_H
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#define EVERGREEND_H
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/* Registers */
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#define CC_GC_SHADER_PIPE_CONFIG 0x8950
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
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#define CGTS_SYS_TCC_DISABLE 0x3F90
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#define CGTS_TCC_DISABLE 0x9148
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#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
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#define CGTS_USER_TCC_DISABLE 0x914C
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#define CONFIG_MEMSIZE 0x5428
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1<<28)
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#define CP_PFP_HALT (1<<26)
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#define CP_ME_RAM_DATA 0xC160
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#define CP_ME_RAM_RADDR 0xC158
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#define CP_ME_RAM_WADDR 0xC15C
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#define CP_MEQ_THRESHOLDS 0x8764
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#define STQ_SPLIT(x) ((x) << 0)
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#define CP_PERFMON_CNTL 0x87FC
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#define CP_PFP_UCODE_ADDR 0xC150
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#define CP_PFP_UCODE_DATA 0xC154
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#define CP_QUEUE_THRESHOLDS 0x8760
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#define ROQ_IB1_START(x) ((x) << 0)
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#define ROQ_IB2_START(x) ((x) << 8)
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#define CP_RB_CNTL 0xC104
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#define RB_BUFSZ(x) ((x)<<0)
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#define RB_BLKSZ(x) ((x)<<8)
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#define RB_NO_UPDATE (1<<27)
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#define RB_RPTR_WR_ENA (1<<31)
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#define BUF_SWAP_32BIT (2 << 16)
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#define CP_RB_RPTR 0x8700
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#define CP_RB_RPTR_ADDR 0xC10C
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#define CP_RB_RPTR_ADDR_HI 0xC110
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#define CP_RB_RPTR_WR 0xC108
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#define CP_RB_WPTR 0xC114
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#define CP_RB_WPTR_ADDR 0xC118
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#define CP_RB_WPTR_ADDR_HI 0xC11C
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#define CP_RB_WPTR_DELAY 0x8704
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#define CP_SEM_WAIT_TIMER 0x85BC
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#define GC_USER_SHADER_PIPE_CONFIG 0x8954
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#define INACTIVE_QD_PIPES(x) ((x) << 8)
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#define INACTIVE_QD_PIPES_MASK 0x0000FF00
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#define INACTIVE_SIMDS(x) ((x) << 16)
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#define INACTIVE_SIMDS_MASK 0x00FF0000
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define GRBM_SOFT_RESET 0x8020
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#define SOFT_RESET_CP (1<<0)
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#define GRBM_STATUS 0x8010
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#define CMDFIFO_AVAIL_MASK 0x0000000F
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#define GUI_ACTIVE (1<<31)
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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#define HDP_NONSURFACE_INFO 0x2C08
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#define HDP_NONSURFACE_SIZE 0x2C0C
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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
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#define HDP_TILING_CONFIG 0x2F3C
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x00003000
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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#define NOOFRANK_SHIFT 2
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#define NOOFRANK_MASK 0x00000004
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#define NOOFROWS_SHIFT 3
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#define NOOFROWS_MASK 0x00000038
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#define NOOFCOLS_SHIFT 6
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#define NOOFCOLS_MASK 0x000000C0
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#define CHANSIZE_SHIFT 8
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#define CHANSIZE_MASK 0x00000100
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#define BURSTLENGTH_SHIFT 9
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#define BURSTLENGTH_MASK 0x00000200
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#define CHANSIZE_OVERRIDE (1 << 11)
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#define MC_VM_AGP_TOP 0x2028
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#define MC_VM_AGP_BOT 0x202C
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#define MC_VM_AGP_BASE 0x2030
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#define MC_VM_FB_LOCATION 0x2024
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#define MC_VM_MB_L1_TLB0_CNTL 0x2234
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#define MC_VM_MB_L1_TLB1_CNTL 0x2238
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#define MC_VM_MB_L1_TLB2_CNTL 0x223C
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#define MC_VM_MB_L1_TLB3_CNTL 0x2240
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#define ENABLE_L1_TLB (1 << 0)
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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
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#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
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#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
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#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
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#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
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#define MC_VM_MD_L1_TLB0_CNTL 0x2654
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#define MC_VM_MD_L1_TLB1_CNTL 0x2658
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#define MC_VM_MD_L1_TLB2_CNTL 0x265C
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#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
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#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
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#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
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#define PA_CL_ENHANCE 0x8A14
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#define CLIP_VTX_REORDER_ENA (1 << 0)
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#define NUM_CLIP_SEQ(x) ((x) << 1)
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#define PA_SC_AA_CONFIG 0x28C04
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#define PA_SC_CLIPRECT_RULE 0x2820C
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#define PA_SC_EDGERULE 0x28230
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#define PA_SC_FIFO_SIZE 0x8BCC
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#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
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#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
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#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
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#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
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#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
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#define PA_SC_LINE_STIPPLE 0x28A0C
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#define PA_SC_LINE_STIPPLE_STATE 0x8B10
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#define SCRATCH_REG0 0x8500
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#define SCRATCH_REG1 0x8504
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#define SCRATCH_REG2 0x8508
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#define SCRATCH_REG3 0x850C
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#define SCRATCH_REG4 0x8510
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#define SCRATCH_REG5 0x8514
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#define SCRATCH_REG6 0x8518
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#define SCRATCH_REG7 0x851C
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#define SCRATCH_UMSK 0x8540
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#define SCRATCH_ADDR 0x8544
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#define SMX_DC_CTL0 0xA020
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#define USE_HASH_FUNCTION (1 << 0)
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#define CACHE_DEPTH(x) ((x) << 1)
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#define FLUSH_ALL_ON_EVENT (1 << 10)
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#define STALL_ON_EVENT (1 << 11)
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#define SMX_EVENT_CTL 0xA02C
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#define ES_FLUSH_CTL(x) ((x) << 0)
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#define GS_FLUSH_CTL(x) ((x) << 3)
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#define ACK_FLUSH_CTL(x) ((x) << 6)
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#define SYNC_FLUSH_CTL (1 << 8)
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#define SPI_CONFIG_CNTL 0x9100
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#define GPR_WRITE_PRIORITY(x) ((x) << 0)
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#define SPI_CONFIG_CNTL_1 0x913C
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#define VTX_DONE_DELAY(x) ((x) << 0)
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#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
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#define SPI_INPUT_Z 0x286D8
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#define SPI_PS_IN_CONTROL_0 0x286CC
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#define NUM_INTERP(x) ((x)<<0)
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#define POSITION_ENA (1<<8)
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#define POSITION_CENTROID (1<<9)
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#define POSITION_ADDR(x) ((x)<<10)
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#define PARAM_GEN(x) ((x)<<15)
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#define PARAM_GEN_ADDR(x) ((x)<<19)
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#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
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#define PERSP_GRADIENT_ENA (1<<28)
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#define LINEAR_GRADIENT_ENA (1<<29)
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#define POSITION_SAMPLE (1<<30)
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#define BARYC_AT_SAMPLE_ENA (1<<31)
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#define SQ_CONFIG 0x8C00
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#define VC_ENABLE (1 << 0)
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#define EXPORT_SRC_C (1 << 1)
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#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
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#define NUM_PS_GPRS(x) ((x) << 0)
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#define NUM_VS_GPRS(x) ((x) << 16)
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#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
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#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
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#define NUM_GS_GPRS(x) ((x) << 0)
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#define NUM_ES_GPRS(x) ((x) << 16)
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#define SQ_MS_FIFO_SIZES 0x8CF0
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#define CACHE_FIFO_SIZE(x) ((x) << 0)
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#define FETCH_FIFO_HIWATER(x) ((x) << 8)
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#define DONE_FIFO_HIWATER(x) ((x) << 16)
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#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
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#define SX_DEBUG_1 0x9058
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#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
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#define SX_EXPORT_BUFFER_SIZES 0x900C
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#define COLOR_BUFFER_SIZE(x) ((x) << 0)
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#define POSITION_BUFFER_SIZE(x) ((x) << 8)
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#define SMX_BUFFER_SIZE(x) ((x) << 16)
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#define SX_MISC 0x28350
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#define TA_CNTL_AUX 0x9508
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#define DISABLE_CUBE_WRAP (1 << 0)
|
||||
#define DISABLE_CUBE_ANISO (1 << 1)
|
||||
#define SYNC_GRADIENT (1 << 24)
|
||||
#define SYNC_WALKER (1 << 25)
|
||||
#define SYNC_ALIGNER (1 << 26)
|
||||
|
||||
#define VGT_CACHE_INVALIDATION 0x88C4
|
||||
#define CACHE_INVALIDATION(x) ((x)<<0)
|
||||
#define VC_ONLY 0
|
||||
#define TC_ONLY 1
|
||||
#define VC_AND_TC 2
|
||||
#define AUTO_INVLD_EN(x) ((x) << 6)
|
||||
#define NO_AUTO 0
|
||||
#define ES_AUTO 1
|
||||
#define GS_AUTO 2
|
||||
#define ES_AND_GS_AUTO 3
|
||||
#define VGT_GS_VERTEX_REUSE 0x88D4
|
||||
#define VGT_NUM_INSTANCES 0x8974
|
||||
#define VGT_OUT_DEALLOC_CNTL 0x28C5C
|
||||
#define DEALLOC_DIST_MASK 0x0000007F
|
||||
#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
|
||||
#define VTX_REUSE_DEPTH_MASK 0x000000FF
|
||||
|
||||
#define VM_CONTEXT0_CNTL 0x1410
|
||||
#define ENABLE_CONTEXT (1 << 0)
|
||||
#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
|
||||
#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
|
||||
#define VM_CONTEXT1_CNTL 0x1414
|
||||
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
|
||||
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
|
||||
#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
|
||||
#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
|
||||
#define RESPONSE_TYPE_MASK 0x000000F0
|
||||
#define RESPONSE_TYPE_SHIFT 4
|
||||
#define VM_L2_CNTL 0x1400
|
||||
#define ENABLE_L2_CACHE (1 << 0)
|
||||
#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
|
||||
#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
|
||||
#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
|
||||
#define VM_L2_CNTL2 0x1404
|
||||
#define INVALIDATE_ALL_L1_TLBS (1 << 0)
|
||||
#define INVALIDATE_L2_CACHE (1 << 1)
|
||||
#define VM_L2_CNTL3 0x1408
|
||||
#define BANK_SELECT(x) ((x) << 0)
|
||||
#define CACHE_UPDATE_MODE(x) ((x) << 6)
|
||||
#define VM_L2_STATUS 0x140C
|
||||
#define L2_BUSY (1 << 0)
|
||||
|
||||
#define WAIT_UNTIL 0x8040
|
||||
|
||||
#define SRBM_STATUS 0x0E50
|
||||
|
||||
#endif
|
||||
|
|
@ -639,7 +639,7 @@ static struct radeon_asic evergreen_asic = {
|
|||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
|
||||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = NULL,
|
||||
.ring_ib_execute = NULL,
|
||||
|
|
|
|||
|
|
@ -281,6 +281,7 @@ int rv770_resume(struct radeon_device *rdev);
|
|||
/*
|
||||
* evergreen
|
||||
*/
|
||||
void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
int evergreen_init(struct radeon_device *rdev);
|
||||
void evergreen_fini(struct radeon_device *rdev);
|
||||
int evergreen_suspend(struct radeon_device *rdev);
|
||||
|
|
|
|||
Loading…
Reference in a new issue