cxgb4: introduce fw_filter2_wr to prepare for L3/L4 rewrite support
Update driver to use new fw_filter2_wr in order to support rewrite of L3/L4 header fields via filters. Query FW_PARAMS_PARAM_DEV_FILTER2_WR to check whether FW supports this new wr. Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Kumar Sanghvi
David S. Miller
parent
202187c34c
commit
0ff9099461
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@ -367,6 +367,7 @@ struct adapter_params {
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unsigned int max_ird_adapter; /* Max read depth per adapter */
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bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
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u8 fw_caps_support; /* 32-bit Port Capabilities */
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bool filter2_wr_support; /* FW support for FILTER2_WR */
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/* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
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* used by the Port
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@ -1064,10 +1065,19 @@ struct ch_filter_specification {
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uint32_t newdmac:1; /* rewrite destination MAC address */
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uint32_t newsmac:1; /* rewrite source MAC address */
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uint32_t newvlan:2; /* rewrite VLAN Tag */
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uint32_t nat_mode:3; /* specify NAT operation mode */
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uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
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uint8_t smac[ETH_ALEN]; /* new source MAC address */
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uint16_t vlan; /* VLAN Tag to insert */
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u8 nat_lip[16]; /* local IP to use after NAT'ing */
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u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
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u16 nat_lport; /* local port to use after NAT'ing */
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u16 nat_fport; /* foreign port to use after NAT'ing */
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/* reservation for future additions */
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u8 rsvd[24];
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/* Filter rule value/mask pairs.
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*/
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struct ch_filter_tuple val;
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@ -313,7 +313,7 @@ static int del_filter_wr(struct adapter *adapter, int fidx)
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int set_filter_wr(struct adapter *adapter, int fidx)
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{
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struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
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struct fw_filter_wr *fwr;
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struct fw_filter2_wr *fwr;
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struct sk_buff *skb;
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skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
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@ -359,7 +359,10 @@ int set_filter_wr(struct adapter *adapter, int fidx)
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* filter specification structure but for now it's easiest to simply
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* put this fairly direct code in line ...
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*/
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fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
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if (adapter->params.filter2_wr_support)
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fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER2_WR));
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else
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fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
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fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr) / 16));
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fwr->tid_to_iq =
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htonl(FW_FILTER_WR_TID_V(f->tid) |
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@ -421,6 +424,18 @@ int set_filter_wr(struct adapter *adapter, int fidx)
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fwr->fp = htons(f->fs.val.fport);
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fwr->fpm = htons(f->fs.mask.fport);
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if (adapter->params.filter2_wr_support) {
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fwr->natmode_to_ulp_type =
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FW_FILTER2_WR_ULP_TYPE_V(f->fs.nat_mode ?
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ULP_MODE_TCPDDP :
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ULP_MODE_NONE) |
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FW_FILTER2_WR_NATMODE_V(f->fs.nat_mode);
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memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
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memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
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fwr->newlport = htons(f->fs.nat_lport);
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fwr->newfport = htons(f->fs.nat_fport);
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}
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/* Mark the filter as "pending" and ship off the Filter Work Request.
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* When we get the Work Request Reply we'll clear the pending status.
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*/
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@ -3910,6 +3910,16 @@ static int adap_init0(struct adapter *adap)
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1, params, val);
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adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
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/* See if FW supports FW_FILTER2 work request */
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if (is_t4(adap->params.chip)) {
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adap->params.filter2_wr_support = 0;
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} else {
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params[0] = FW_PARAM_DEV(FILTER2_WR);
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ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
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1, params, val);
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adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
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}
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/*
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* Get device capabilities so we can determine what resources we need
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* to manage.
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@ -105,7 +105,8 @@ enum fw_wr_opcodes {
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FW_ISCSI_TX_DATA_WR = 0x45,
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FW_PTP_TX_PKT_WR = 0x46,
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FW_CRYPTO_LOOKASIDE_WR = 0X6d,
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FW_LASTC2E_WR = 0x70
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FW_LASTC2E_WR = 0x70,
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FW_FILTER2_WR = 0x77
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};
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struct fw_wr_hdr {
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@ -201,6 +202,51 @@ struct fw_filter_wr {
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__u8 sma[6];
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};
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struct fw_filter2_wr {
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__be32 op_pkd;
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__be32 len16_pkd;
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__be64 r3;
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__be32 tid_to_iq;
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__be32 del_filter_to_l2tix;
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__be16 ethtype;
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__be16 ethtypem;
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__u8 frag_to_ovlan_vldm;
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__u8 smac_sel;
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__be16 rx_chan_rx_rpl_iq;
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__be32 maci_to_matchtypem;
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__u8 ptcl;
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__u8 ptclm;
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__u8 ttyp;
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__u8 ttypm;
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__be16 ivlan;
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__be16 ivlanm;
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__be16 ovlan;
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__be16 ovlanm;
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__u8 lip[16];
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__u8 lipm[16];
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__u8 fip[16];
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__u8 fipm[16];
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__be16 lp;
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__be16 lpm;
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__be16 fp;
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__be16 fpm;
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__be16 r7;
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__u8 sma[6];
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__be16 r8;
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__u8 filter_type_swapmac;
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__u8 natmode_to_ulp_type;
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__be16 newlport;
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__be16 newfport;
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__u8 newlip[16];
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__u8 newfip[16];
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__be32 natseqcheck;
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__be32 r9;
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__be64 r10;
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__be64 r11;
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__be64 r12;
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__be64 r13;
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};
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#define FW_FILTER_WR_TID_S 12
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#define FW_FILTER_WR_TID_M 0xfffff
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#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
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@ -385,6 +431,32 @@ struct fw_filter_wr {
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#define FW_FILTER_WR_RX_RPL_IQ_G(x) \
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(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
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#define FW_FILTER2_WR_FILTER_TYPE_S 1
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#define FW_FILTER2_WR_FILTER_TYPE_M 0x1
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#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
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#define FW_FILTER2_WR_FILTER_TYPE_G(x) \
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(((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
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#define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U)
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#define FW_FILTER2_WR_NATMODE_S 5
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#define FW_FILTER2_WR_NATMODE_M 0x7
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#define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)
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#define FW_FILTER2_WR_NATMODE_G(x) \
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(((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
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#define FW_FILTER2_WR_NATFLAGCHECK_S 4
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#define FW_FILTER2_WR_NATFLAGCHECK_M 0x1
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#define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
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#define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
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(((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
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#define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U)
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#define FW_FILTER2_WR_ULP_TYPE_S 0
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#define FW_FILTER2_WR_ULP_TYPE_M 0xf
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#define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)
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#define FW_FILTER2_WR_ULP_TYPE_G(x) \
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(((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
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#define FW_FILTER_WR_MACI_S 23
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#define FW_FILTER_WR_MACI_M 0x1ff
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#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
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@ -1127,6 +1199,7 @@ enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
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FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
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FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
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FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
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FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
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};
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