drm/tegra: dsi: Implement host transfers
Add support for sending MIPI DSI command packets from the host to a peripheral. This is required for panels that need configuration before they accept video data. Signed-off-by: Thierry Reding <treding@nvidia.com>hifive-unleashed-5.1
Thierry Reding
parent
e94236cde4
commit
0fffdf6ca9
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@ -993,6 +993,272 @@ static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
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return 0;
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}
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static const char * const error_report[16] = {
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"SoT Error",
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"SoT Sync Error",
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"EoT Sync Error",
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"Escape Mode Entry Command Error",
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"Low-Power Transmit Sync Error",
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"Peripheral Timeout Error",
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"False Control Error",
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"Contention Detected",
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"ECC Error, single-bit",
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"ECC Error, multi-bit",
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"Checksum Error",
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"DSI Data Type Not Recognized",
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"DSI VC ID Invalid",
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"Invalid Transmission Length",
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"Reserved",
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"DSI Protocol Violation",
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};
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static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
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const struct mipi_dsi_msg *msg,
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size_t count)
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{
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u8 *rx = msg->rx_buf;
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unsigned int i, j, k;
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size_t size = 0;
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u16 errors;
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u32 value;
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/* read and parse packet header */
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value = tegra_dsi_readl(dsi, DSI_RD_DATA);
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switch (value & 0x3f) {
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case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
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errors = (value >> 8) & 0xffff;
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dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
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errors);
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for (i = 0; i < ARRAY_SIZE(error_report); i++)
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if (errors & BIT(i))
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dev_dbg(dsi->dev, " %2u: %s\n", i,
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error_report[i]);
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break;
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case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
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rx[0] = (value >> 8) & 0xff;
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size = 1;
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break;
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case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
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rx[0] = (value >> 8) & 0xff;
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rx[1] = (value >> 16) & 0xff;
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size = 2;
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break;
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case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
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size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
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break;
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case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
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size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
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break;
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default:
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dev_err(dsi->dev, "unhandled response type: %02x\n",
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value & 0x3f);
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return -EPROTO;
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}
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size = min(size, msg->rx_len);
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if (msg->rx_buf && size > 0) {
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for (i = 0, j = 0; i < count - 1; i++, j += 4) {
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u8 *rx = msg->rx_buf + j;
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value = tegra_dsi_readl(dsi, DSI_RD_DATA);
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for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
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rx[j + k] = (value >> (k << 3)) & 0xff;
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}
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}
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return size;
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}
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static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
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{
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tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
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timeout = jiffies + msecs_to_jiffies(timeout);
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while (time_before(jiffies, timeout)) {
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u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
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if ((value & DSI_TRIGGER_HOST) == 0)
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return 0;
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usleep_range(1000, 2000);
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}
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DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
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return -ETIMEDOUT;
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}
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static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
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unsigned long timeout)
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{
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
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u8 count = value & 0x1f;
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if (count > 0)
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return count;
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usleep_range(1000, 2000);
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}
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DRM_DEBUG_KMS("peripheral returned no data\n");
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return -ETIMEDOUT;
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}
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static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
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const void *buffer, size_t size)
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{
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const u8 *buf = buffer;
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size_t i, j;
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u32 value;
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for (j = 0; j < size; j += 4) {
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value = 0;
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for (i = 0; i < 4 && j + i < size; i++)
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value |= buf[j + i] << (i << 3);
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tegra_dsi_writel(dsi, value, DSI_WR_DATA);
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}
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}
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static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
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const struct mipi_dsi_msg *msg)
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{
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struct tegra_dsi *dsi = host_to_tegra(host);
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struct mipi_dsi_packet packet;
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const u8 *header;
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size_t count;
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ssize_t err;
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u32 value;
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err = mipi_dsi_create_packet(&packet, msg);
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if (err < 0)
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return err;
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header = packet.header;
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/* maximum FIFO depth is 1920 words */
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if (packet.size > dsi->video_fifo_depth * 4)
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return -ENOSPC;
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/* reset underflow/overflow flags */
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value = tegra_dsi_readl(dsi, DSI_STATUS);
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if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
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value = DSI_HOST_CONTROL_FIFO_RESET;
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tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
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usleep_range(10, 20);
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}
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value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
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value |= DSI_POWER_CONTROL_ENABLE;
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tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
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usleep_range(5000, 10000);
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value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
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DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
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if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
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value |= DSI_HOST_CONTROL_HS;
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/*
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* The host FIFO has a maximum of 64 words, so larger transmissions
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* need to use the video FIFO.
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*/
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if (packet.size > dsi->host_fifo_depth * 4)
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value |= DSI_HOST_CONTROL_FIFO_SEL;
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tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
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/*
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* For reads and messages with explicitly requested ACK, generate a
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* BTA sequence after the transmission of the packet.
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*/
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if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
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(msg->rx_buf && msg->rx_len > 0)) {
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value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
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value |= DSI_HOST_CONTROL_PKT_BTA;
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tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
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}
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value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
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tegra_dsi_writel(dsi, value, DSI_CONTROL);
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/* write packet header, ECC is generated by hardware */
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value = header[2] << 16 | header[1] << 8 | header[0];
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tegra_dsi_writel(dsi, value, DSI_WR_DATA);
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/* write payload (if any) */
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if (packet.payload_length > 0)
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tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
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packet.payload_length);
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err = tegra_dsi_transmit(dsi, 250);
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if (err < 0)
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return err;
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if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
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(msg->rx_buf && msg->rx_len > 0)) {
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err = tegra_dsi_wait_for_response(dsi, 250);
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if (err < 0)
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return err;
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count = err;
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value = tegra_dsi_readl(dsi, DSI_RD_DATA);
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switch (value) {
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case 0x84:
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/*
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dev_dbg(dsi->dev, "ACK\n");
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*/
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break;
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case 0x87:
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/*
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dev_dbg(dsi->dev, "ESCAPE\n");
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*/
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break;
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default:
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dev_err(dsi->dev, "unknown status: %08x\n", value);
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break;
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}
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if (count > 1) {
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err = tegra_dsi_read_response(dsi, msg, count);
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if (err < 0)
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dev_err(dsi->dev,
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"failed to parse response: %zd\n",
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err);
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else {
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/*
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* For read commands, return the number of
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* bytes returned by the peripheral.
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*/
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count = err;
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}
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}
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} else {
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/*
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* For write commands, we have transmitted the 4-byte header
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* plus the variable-length payload.
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*/
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count = 4 + packet.payload_length;
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}
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return count;
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}
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static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
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{
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struct clk *parent;
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@ -1069,6 +1335,7 @@ static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
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static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
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.attach = tegra_dsi_host_attach,
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.detach = tegra_dsi_host_detach,
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.transfer = tegra_dsi_host_transfer,
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};
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static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
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@ -21,9 +21,16 @@
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#define DSI_INT_STATUS 0x0d
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#define DSI_INT_MASK 0x0e
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#define DSI_HOST_CONTROL 0x0f
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#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
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#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
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#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
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#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
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#define DSI_HOST_CONTROL_RAW (1 << 6)
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#define DSI_HOST_CONTROL_HS (1 << 5)
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#define DSI_HOST_CONTROL_BTA (1 << 2)
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#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
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#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
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#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
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#define DSI_HOST_CONTROL_CS (1 << 1)
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#define DSI_HOST_CONTROL_ECC (1 << 0)
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#define DSI_CONTROL 0x10
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@ -39,9 +46,13 @@
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#define DSI_SOL_DELAY 0x11
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#define DSI_MAX_THRESHOLD 0x12
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#define DSI_TRIGGER 0x13
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#define DSI_TRIGGER_HOST (1 << 1)
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#define DSI_TRIGGER_VIDEO (1 << 0)
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#define DSI_TX_CRC 0x14
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#define DSI_STATUS 0x15
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#define DSI_STATUS_IDLE (1 << 10)
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#define DSI_STATUS_UNDERFLOW (1 << 9)
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#define DSI_STATUS_OVERFLOW (1 << 8)
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#define DSI_INIT_SEQ_CONTROL 0x1a
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#define DSI_INIT_SEQ_DATA_0 0x1b
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#define DSI_INIT_SEQ_DATA_1 0x1c
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