diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 277a6a8010e8..0f21f7c77533 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -38,82 +38,86 @@
 	bus_wcore_opp_table: opp_table2 {
 		compatible = "operating-points-v2";
 
+		/* derived from 532MHz MPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <84000000>;
+			opp-hz = /bits/ 64 <88700000>;
 			opp-microvolt = <925000 925000 1400000>;
 		};
 		opp01 {
-			opp-hz = /bits/ 64 <111000000>;
+			opp-hz = /bits/ 64 <133000000>;
 			opp-microvolt = <950000 950000 1400000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <222000000>;
+			opp-hz = /bits/ 64 <177400000>;
 			opp-microvolt = <950000 950000 1400000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <333000000>;
+			opp-hz = /bits/ 64 <266000000>;
 			opp-microvolt = <950000 950000 1400000>;
 		};
 		opp04 {
-			opp-hz = /bits/ 64 <400000000>;
-			opp-microvolt = <987500 987500 1400000>;
+			opp-hz = /bits/ 64 <532000000>;
+			opp-microvolt = <1000000 1000000 1400000>;
 		};
 	};
 
 	bus_noc_opp_table: opp_table3 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <67000000>;
+			opp-hz = /bits/ 64 <66600000>;
 		};
 		opp01 {
-			opp-hz = /bits/ 64 <75000000>;
+			opp-hz = /bits/ 64 <74000000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <86000000>;
+			opp-hz = /bits/ 64 <83250000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <100000000>;
+			opp-hz = /bits/ 64 <111000000>;
 		};
 	};
 
 	bus_fsys_apb_opp_table: opp_table4 {
 		compatible = "operating-points-v2";
-		opp-shared;
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <100000000>;
+			opp-hz = /bits/ 64 <111000000>;
 		};
 		opp01 {
-			opp-hz = /bits/ 64 <200000000>;
+			opp-hz = /bits/ 64 <222000000>;
 		};
 	};
 
 	bus_fsys2_opp_table: opp_table5 {
 		compatible = "operating-points-v2";
 
+		/* derived from 600MHz DPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <75000000>;
 		};
 		opp01 {
-			opp-hz = /bits/ 64 <100000000>;
+			opp-hz = /bits/ 64 <120000000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <150000000>;
+			opp-hz = /bits/ 64 <200000000>;
 		};
 	};
 
 	bus_mfc_opp_table: opp_table6 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <96000000>;
+			opp-hz = /bits/ 64 <83250000>;
 		};
 		opp01 {
 			opp-hz = /bits/ 64 <111000000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <167000000>;
+			opp-hz = /bits/ 64 <166500000>;
 		};
 		opp03 {
 			opp-hz = /bits/ 64 <222000000>;
@@ -126,8 +130,9 @@
 	bus_gen_opp_table: opp_table7 {
 		compatible = "operating-points-v2";
 
+		/* derived from 532MHz MPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <89000000>;
+			opp-hz = /bits/ 64 <88700000>;
 		};
 		opp01 {
 			opp-hz = /bits/ 64 <133000000>;
@@ -136,32 +141,34 @@
 			opp-hz = /bits/ 64 <178000000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <267000000>;
+			opp-hz = /bits/ 64 <266000000>;
 		};
 	};
 
 	bus_peri_opp_table: opp_table8 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <67000000>;
+			opp-hz = /bits/ 64 <66600000>;
 		};
 	};
 
 	bus_g2d_opp_table: opp_table9 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <84000000>;
+			opp-hz = /bits/ 64 <83250000>;
 		};
 		opp01 {
-			opp-hz = /bits/ 64 <167000000>;
+			opp-hz = /bits/ 64 <111000000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <222000000>;
+			opp-hz = /bits/ 64 <166500000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <300000000>;
+			opp-hz = /bits/ 64 <222000000>;
 		};
 		opp04 {
 			opp-hz = /bits/ 64 <333000000>;
@@ -171,8 +178,9 @@
 	bus_g2d_acp_opp_table: opp_table10 {
 		compatible = "operating-points-v2";
 
+		/* derived from 532MHz MPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <67000000>;
+			opp-hz = /bits/ 64 <66500000>;
 		};
 		opp01 {
 			opp-hz = /bits/ 64 <133000000>;
@@ -181,13 +189,14 @@
 			opp-hz = /bits/ 64 <178000000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <267000000>;
+			opp-hz = /bits/ 64 <266000000>;
 		};
 	};
 
 	bus_jpeg_opp_table: opp_table11 {
 		compatible = "operating-points-v2";
 
+		/* derived from 600MHz DPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <75000000>;
 		};
@@ -205,23 +214,25 @@
 	bus_jpeg_apb_opp_table: opp_table12 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
-			opp-hz = /bits/ 64 <84000000>;
+			opp-hz = /bits/ 64 <83250000>;
 		};
 		opp01 {
 			opp-hz = /bits/ 64 <111000000>;
 		};
 		opp02 {
-			opp-hz = /bits/ 64 <134000000>;
+			opp-hz = /bits/ 64 <133000000>;
 		};
 		opp03 {
-			opp-hz = /bits/ 64 <167000000>;
+			opp-hz = /bits/ 64 <166500000>;
 		};
 	};
 
 	bus_disp1_fimd_opp_table: opp_table13 {
 		compatible = "operating-points-v2";
 
+		/* derived from 600MHz DPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <120000000>;
 		};
@@ -233,6 +244,7 @@
 	bus_disp1_opp_table: opp_table14 {
 		compatible = "operating-points-v2";
 
+		/* derived from 600MHz DPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <120000000>;
 		};
@@ -247,6 +259,7 @@
 	bus_gscl_opp_table: opp_table15 {
 		compatible = "operating-points-v2";
 
+		/* derived from 600MHz DPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <150000000>;
 		};
@@ -261,6 +274,7 @@
 	bus_mscl_opp_table: opp_table16 {
 		compatible = "operating-points-v2";
 
+		/* derived from 666MHz CPLL */
 		opp00 {
 			opp-hz = /bits/ 64 <84000000>;
 		};
@@ -274,7 +288,7 @@
 			opp-hz = /bits/ 64 <333000000>;
 		};
 		opp04 {
-			opp-hz = /bits/ 64 <400000000>;
+			opp-hz = /bits/ 64 <666000000>;
 		};
 	};
 
@@ -398,7 +412,7 @@
 };
 
 &bus_fsys {
-	operating-points-v2 = <&bus_fsys_apb_opp_table>;
+	operating-points-v2 = <&bus_fsys2_opp_table>;
 	devfreq = <&bus_wcore>;
 	status = "okay";
 };