MIPS: Lemote 2F: Add PCI support
PCI support for the Fuloong 2E and Lemote Loongson 2F family machines is mostly identical with the exception of CS5536 support. Rename ops-fuloong2e.c to ops-loongson2.c then add the CS5536 support to share most of the source code among Loongson machines. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: zhangfx@lemote.com Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Nicholas Mc Guire <hofrat@hofr.at> Cc: Arnaud Patard <apatard@mandriva.com> Cc: loongson-dev@googlegroups.com Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Wu Zhangjin
Ralf Baechle
parent
22c21003a9
commit
1032bce3ef
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@ -28,7 +28,8 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
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obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
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obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
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obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
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obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o
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obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
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obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
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obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
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obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
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obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
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@ -0,0 +1,160 @@
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/*
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* Copyright (C) 2008 Lemote Technology
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* Copyright (C) 2004 ICT CAS
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* Author: Li xiaoyu, lixy@ict.ac.cn
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <loongson.h>
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#include <cs5536/cs5536.h>
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#include <cs5536/cs5536_pci.h>
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/* PCI interrupt pins
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*
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* These should not be changed, or you should consider loongson2f interrupt
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* register and your pci card dispatch
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*/
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#define PCIA 4
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#define PCIB 5
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#define PCIC 6
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#define PCID 7
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/* all the pci device has the PCIA pin, check the datasheet. */
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static char irq_tab[][5] __initdata = {
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/* INTA INTB INTC INTD */
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{0, 0, 0, 0, 0}, /* 11: Unused */
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{0, 0, 0, 0, 0}, /* 12: Unused */
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{0, 0, 0, 0, 0}, /* 13: Unused */
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{0, 0, 0, 0, 0}, /* 14: Unused */
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{0, 0, 0, 0, 0}, /* 15: Unused */
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{0, 0, 0, 0, 0}, /* 16: Unused */
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{0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
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{0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
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{0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
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{0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
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{0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
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{0, 0, 0, 0, 0}, /* 22: Unused */
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{0, 0, 0, 0, 0}, /* 23: Unused */
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{0, 0, 0, 0, 0}, /* 24: Unused */
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{0, 0, 0, 0, 0}, /* 25: Unused */
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{0, 0, 0, 0, 0}, /* 26: Unused */
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{0, 0, 0, 0, 0}, /* 27: Unused */
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int virq;
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if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
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&& (PCI_SLOT(dev->devfn) < 32)) {
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virq = irq_tab[slot][pin];
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printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
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virq + LOONGSON_IRQ_BASE);
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if (virq != 0)
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return LOONGSON_IRQ_BASE + virq;
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else
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return 0;
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} else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
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switch (PCI_FUNC(dev->devfn)) {
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case 2:
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
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CS5536_IDE_INTR);
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return CS5536_IDE_INTR; /* for IDE */
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case 3:
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
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CS5536_ACC_INTR);
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return CS5536_ACC_INTR; /* for AUDIO */
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case 4: /* for OHCI */
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case 5: /* for EHCI */
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case 6: /* for UDC */
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case 7: /* for OTG */
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
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CS5536_USB_INTR);
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return CS5536_USB_INTR;
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}
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return dev->irq;
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} else {
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printk(KERN_INFO " strange pci slot number.\n");
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return 0;
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}
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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/* CS5536 SPEC. fixup */
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static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
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{
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/* the uart1 and uart2 interrupt in PIC is enabled as default */
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pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
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pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
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}
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static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
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{
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/* setting the mutex pin as IDE function */
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pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
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CS5536_IDE_FLASH_SIGNATURE);
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}
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static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
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{
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/* enable the AUDIO interrupt in PIC */
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pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
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}
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static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
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{
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/* enable the OHCI interrupt in PIC */
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/* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
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pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
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}
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static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
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{
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u32 hi, lo;
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/* Serial short detect enable */
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_rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
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_wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
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/* setting the USB2.0 micro frame length */
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pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
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}
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static void __init loongson_nec_fixup(struct pci_dev *pdev)
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{
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unsigned int val;
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pci_read_config_dword(pdev, 0xe0, &val);
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/* Only 2 port be used */
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pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
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loongson_cs5536_isa_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
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loongson_cs5536_ohci_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
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loongson_cs5536_ehci_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
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loongson_cs5536_acc_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
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loongson_cs5536_ide_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
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loongson_nec_fixup);
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@ -20,6 +20,11 @@
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#include <loongson.h>
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#ifdef CONFIG_CS5536
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#include <cs5536/cs5536_pci.h>
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#include <cs5536/cs5536.h>
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#endif
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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@ -43,6 +48,29 @@ static int loongson_pcibios_config_access(unsigned char access_type,
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int reg = where & ~3;
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if (busnum == 0) {
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/* board-specific part,currently,only fuloong2f,yeeloong2f
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* use CS5536, fuloong2e use via686b, gdium has no
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* south bridge
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*/
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#ifdef CONFIG_CS5536
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/* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
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* access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
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* PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
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* will not go this branch, but the others. so, no calling dead
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* loop here.
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*/
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if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
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switch (access_type) {
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case PCI_ACCESS_READ:
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*data = cs5536_pci_conf_read4(function, reg);
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break;
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case PCI_ACCESS_WRITE:
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cs5536_pci_conf_write4(function, reg, *data);
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break;
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}
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return 0;
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}
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#endif
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/* Type 0 configuration for onboard PCI bus */
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if (device > MAX_DEV_NUM)
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return -1;
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@ -152,3 +180,29 @@ struct pci_ops loongson_pci_ops = {
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.read = loongson_pcibios_read,
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.write = loongson_pcibios_write
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};
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#ifdef CONFIG_CS5536
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void _rdmsr(u32 msr, u32 *hi, u32 *lo)
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{
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struct pci_bus bus = {
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.number = PCI_BUS_CS5536
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};
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u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
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loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
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loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
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loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
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}
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EXPORT_SYMBOL(_rdmsr);
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void _wrmsr(u32 msr, u32 hi, u32 lo)
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{
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struct pci_bus bus = {
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.number = PCI_BUS_CS5536
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};
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u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
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loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
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loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
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loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
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}
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EXPORT_SYMBOL(_wrmsr);
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#endif
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