perf_counter: powerpc: Implement generalized cache events for POWER processors
This adds tables of event codes for the generalized cache events for all the currently supported powerpc processors: POWER{4,5,5+,6,7} and PPC970*, plus powerpc-specific code to use these tables when a generalized cache event is requested. Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <18992.36430.933526.742969@drongo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
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4da52960fd
commit
106b506c3a
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@ -33,6 +33,9 @@ struct power_pmu {
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u32 flags;
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u32 flags;
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int n_generic;
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int n_generic;
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int *generic_events;
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int *generic_events;
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int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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};
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};
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extern struct power_pmu *ppmu;
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extern struct power_pmu *ppmu;
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@ -856,6 +856,36 @@ static void hw_perf_counter_destroy(struct perf_counter *counter)
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}
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}
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}
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}
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/*
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* Translate a generic cache event config to a raw event code.
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*/
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static int hw_perf_cache_event(u64 config, u64 *eventp)
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{
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unsigned long type, op, result;
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int ev;
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if (!ppmu->cache_events)
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return -EINVAL;
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/* unpack config */
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type = config & 0xff;
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op = (config >> 8) & 0xff;
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result = (config >> 16) & 0xff;
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if (type >= PERF_COUNT_HW_CACHE_MAX ||
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op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ev = (*ppmu->cache_events)[type][op][result];
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if (ev == 0)
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return -EOPNOTSUPP;
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if (ev == -1)
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return -EINVAL;
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*eventp = ev;
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return 0;
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}
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const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
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const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
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{
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{
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u64 ev;
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u64 ev;
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@ -868,13 +898,21 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
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if (!ppmu)
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if (!ppmu)
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return ERR_PTR(-ENXIO);
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return ERR_PTR(-ENXIO);
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if (counter->attr.type != PERF_TYPE_RAW) {
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switch (counter->attr.type) {
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case PERF_TYPE_HARDWARE:
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ev = counter->attr.config;
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ev = counter->attr.config;
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if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
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if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
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return ERR_PTR(-EOPNOTSUPP);
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return ERR_PTR(-EOPNOTSUPP);
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ev = ppmu->generic_events[ev];
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ev = ppmu->generic_events[ev];
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} else {
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break;
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case PERF_TYPE_HW_CACHE:
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err = hw_perf_cache_event(counter->attr.config, &ev);
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if (err)
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return ERR_PTR(err);
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break;
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case PERF_TYPE_RAW:
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ev = counter->attr.config;
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ev = counter->attr.config;
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break;
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}
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}
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counter->hw.config_base = ev;
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counter->hw.config_base = ev;
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counter->hw.idx = 0;
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counter->hw.idx = 0;
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@ -543,6 +543,46 @@ static int p4_generic_events[] = {
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[PERF_COUNT_BRANCH_MISSES] = 0x331, /* PM_BR_MPRED_CR */
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[PERF_COUNT_BRANCH_MISSES] = 0x331, /* PM_BR_MPRED_CR */
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};
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x8c10, 0x3c10 },
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[C(OP_WRITE)] = { 0x7c10, 0xc13 },
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[C(OP_PREFETCH)] = { 0xc35, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { 0, 0 },
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[C(OP_PREFETCH)] = { 0xc34, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x904 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x900 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x330, 0x331 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu power4_pmu = {
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struct power_pmu power4_pmu = {
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.n_counter = 8,
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.n_counter = 8,
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.max_alternatives = 5,
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.max_alternatives = 5,
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@ -554,4 +594,5 @@ struct power_pmu power4_pmu = {
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.disable_pmc = p4_disable_pmc,
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.disable_pmc = p4_disable_pmc,
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.n_generic = ARRAY_SIZE(p4_generic_events),
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.n_generic = ARRAY_SIZE(p4_generic_events),
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.generic_events = p4_generic_events,
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.generic_events = p4_generic_events,
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.cache_events = &power4_cache_events,
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};
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};
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@ -614,6 +614,46 @@ static int power5p_generic_events[] = {
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[PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
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[PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
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};
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x1c10a8, 0x3c1088 },
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[C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 },
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[C(OP_PREFETCH)] = { 0xc70e7, -1 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { 0, 0 },
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[C(OP_PREFETCH)] = { 0xc50c3, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0xc20e4, 0x800c4 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x800c0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x230e4, 0x230e5 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu power5p_pmu = {
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struct power_pmu power5p_pmu = {
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.n_counter = 6,
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.n_counter = 6,
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.max_alternatives = MAX_ALT,
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.max_alternatives = MAX_ALT,
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@ -623,8 +663,9 @@ struct power_pmu power5p_pmu = {
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.get_constraint = power5p_get_constraint,
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.get_constraint = power5p_get_constraint,
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.get_alternatives = power5p_get_alternatives,
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.get_alternatives = power5p_get_alternatives,
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.disable_pmc = power5p_disable_pmc,
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.disable_pmc = power5p_disable_pmc,
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.limited_pmc_event = power5p_limited_pmc_event,
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.flags = PPMU_LIMITED_PMC5_6,
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.n_generic = ARRAY_SIZE(power5p_generic_events),
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.n_generic = ARRAY_SIZE(power5p_generic_events),
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.generic_events = power5p_generic_events,
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.generic_events = power5p_generic_events,
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.flags = PPMU_LIMITED_PMC5_6,
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.cache_events = &power5p_cache_events,
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.limited_pmc_event = power5p_limited_pmc_event,
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};
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};
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@ -556,6 +556,46 @@ static int power5_generic_events[] = {
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[PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
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[PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
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};
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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*/
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static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x4c1090, 0x3c1088 },
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[C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
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[C(OP_PREFETCH)] = { 0xc70e7, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0, 0 },
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},
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[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x3c309b },
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[C(OP_WRITE)] = { 0, 0 },
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[C(OP_PREFETCH)] = { 0xc50c3, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x2c4090, 0x800c4 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x800c0 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x230e4, 0x230e5 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu power5_pmu = {
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struct power_pmu power5_pmu = {
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.n_counter = 6,
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.n_counter = 6,
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.max_alternatives = MAX_ALT,
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.max_alternatives = MAX_ALT,
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@ -567,4 +607,5 @@ struct power_pmu power5_pmu = {
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.disable_pmc = power5_disable_pmc,
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.disable_pmc = power5_disable_pmc,
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.n_generic = ARRAY_SIZE(power5_generic_events),
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.n_generic = ARRAY_SIZE(power5_generic_events),
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.generic_events = power5_generic_events,
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.generic_events = power5_generic_events,
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.cache_events = &power5_cache_events,
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};
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};
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@ -474,6 +474,47 @@ static int power6_generic_events[] = {
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[PERF_COUNT_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
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[PERF_COUNT_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
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};
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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/*
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* Table of generalized cache-related events.
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* 0 means not supported, -1 means nonsensical, other values
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* are event codes.
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* The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
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*/
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static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x80082, 0x80080 },
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[C(OP_WRITE)] = { 0x80086, 0x80088 },
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[C(OP_PREFETCH)] = { 0x810a4, 0 },
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},
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x100056 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { 0x4008c, 0 },
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},
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[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x150730, 0x250532 },
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[C(OP_WRITE)] = { 0x250432, 0x150432 },
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[C(OP_PREFETCH)] = { 0x810a6, 0 },
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},
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x20000e },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0, 0x420ce },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
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[C(OP_READ)] = { 0x430e6, 0x400052 },
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[C(OP_WRITE)] = { -1, -1 },
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[C(OP_PREFETCH)] = { -1, -1 },
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},
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};
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struct power_pmu power6_pmu = {
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struct power_pmu power6_pmu = {
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.n_counter = 6,
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.n_counter = 6,
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.max_alternatives = MAX_ALT,
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.max_alternatives = MAX_ALT,
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@ -483,8 +524,9 @@ struct power_pmu power6_pmu = {
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.get_constraint = p6_get_constraint,
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.get_constraint = p6_get_constraint,
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.get_alternatives = p6_get_alternatives,
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.get_alternatives = p6_get_alternatives,
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.disable_pmc = p6_disable_pmc,
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.disable_pmc = p6_disable_pmc,
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.limited_pmc_event = p6_limited_pmc_event,
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.flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
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.n_generic = ARRAY_SIZE(power6_generic_events),
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.n_generic = ARRAY_SIZE(power6_generic_events),
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.generic_events = power6_generic_events,
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.generic_events = power6_generic_events,
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.flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
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.cache_events = &power6_cache_events,
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.limited_pmc_event = p6_limited_pmc_event,
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};
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};
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@ -302,6 +302,46 @@ static int power7_generic_events[] = {
|
||||||
[PERF_COUNT_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */
|
[PERF_COUNT_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Table of generalized cache-related events.
|
||||||
|
* 0 means not supported, -1 means nonsensical, other values
|
||||||
|
* are event codes.
|
||||||
|
*/
|
||||||
|
static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
||||||
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0x400f0, 0xc880 },
|
||||||
|
[C(OP_WRITE)] = { 0, 0x300f0 },
|
||||||
|
[C(OP_PREFETCH)] = { 0xd8b8, 0 },
|
||||||
|
},
|
||||||
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0x200fc },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { 0x408a, 0 },
|
||||||
|
},
|
||||||
|
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0x6080, 0x6084 },
|
||||||
|
[C(OP_WRITE)] = { 0x6082, 0x6086 },
|
||||||
|
[C(OP_PREFETCH)] = { 0, 0 },
|
||||||
|
},
|
||||||
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0x300fc },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0x400fc },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0x10068, 0x400f6 },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
struct power_pmu power7_pmu = {
|
struct power_pmu power7_pmu = {
|
||||||
.n_counter = 6,
|
.n_counter = 6,
|
||||||
.max_alternatives = MAX_ALT + 1,
|
.max_alternatives = MAX_ALT + 1,
|
||||||
|
@ -313,4 +353,5 @@ struct power_pmu power7_pmu = {
|
||||||
.disable_pmc = power7_disable_pmc,
|
.disable_pmc = power7_disable_pmc,
|
||||||
.n_generic = ARRAY_SIZE(power7_generic_events),
|
.n_generic = ARRAY_SIZE(power7_generic_events),
|
||||||
.generic_events = power7_generic_events,
|
.generic_events = power7_generic_events,
|
||||||
|
.cache_events = &power7_cache_events,
|
||||||
};
|
};
|
||||||
|
|
|
@ -427,6 +427,46 @@ static int ppc970_generic_events[] = {
|
||||||
[PERF_COUNT_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
|
[PERF_COUNT_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Table of generalized cache-related events.
|
||||||
|
* 0 means not supported, -1 means nonsensical, other values
|
||||||
|
* are event codes.
|
||||||
|
*/
|
||||||
|
static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
||||||
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0x8810, 0x3810 },
|
||||||
|
[C(OP_WRITE)] = { 0x7810, 0x813 },
|
||||||
|
[C(OP_PREFETCH)] = { 0x731, 0 },
|
||||||
|
},
|
||||||
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0 },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { 0, 0 },
|
||||||
|
},
|
||||||
|
[C(L2)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0 },
|
||||||
|
[C(OP_WRITE)] = { 0, 0 },
|
||||||
|
[C(OP_PREFETCH)] = { 0x733, 0 },
|
||||||
|
},
|
||||||
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0x704 },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0, 0x700 },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
||||||
|
[C(OP_READ)] = { 0x431, 0x327 },
|
||||||
|
[C(OP_WRITE)] = { -1, -1 },
|
||||||
|
[C(OP_PREFETCH)] = { -1, -1 },
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
struct power_pmu ppc970_pmu = {
|
struct power_pmu ppc970_pmu = {
|
||||||
.n_counter = 8,
|
.n_counter = 8,
|
||||||
.max_alternatives = 2,
|
.max_alternatives = 2,
|
||||||
|
@ -438,4 +478,5 @@ struct power_pmu ppc970_pmu = {
|
||||||
.disable_pmc = p970_disable_pmc,
|
.disable_pmc = p970_disable_pmc,
|
||||||
.n_generic = ARRAY_SIZE(ppc970_generic_events),
|
.n_generic = ARRAY_SIZE(ppc970_generic_events),
|
||||||
.generic_events = ppc970_generic_events,
|
.generic_events = ppc970_generic_events,
|
||||||
|
.cache_events = &ppc970_cache_events,
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in a new issue