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mlxsw: reg: Add Management Pulse Per Second Register 

The MTPPS register provides the device PPS capabilities, configure the PPS
in and out modules and holds the PPS in time stamp.

Signed-off-by: Shalom Toledo <shalomt@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
alistair/sunxi64-5.4-dsi
Shalom Toledo 2019-06-11 18:45:08 +03:00 committed by David S. Miller
parent 55a8b00157
commit 1078645af6
1 changed files with 58 additions and 0 deletions
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58
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -8691,6 +8691,63 @@ static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
MLXSW_REG_MLCR_DURATION_MAX : 0);
}
/* MTPPS - Management Pulse Per Second Register
* --------------------------------------------
* This register provides the device PPS capabilities, configure the PPS in and
* out modules and holds the PPS in time stamp.
*/
#define MLXSW_REG_MTPPS_ID 0x9053
#define MLXSW_REG_MTPPS_LEN 0x3C
MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
/* reg_mtpps_enable
* Enables the PPS functionality the specific pin.
* A boolean variable.
* Access: RW
*/
MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
enum mlxsw_reg_mtpps_pin_mode {
MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
};
/* reg_mtpps_pin_mode
* Pin mode to be used. The mode must comply with the supported modes of the
* requested pin.
* Access: RW
*/
MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
/* reg_mtpps_pin
* Pin to be configured or queried out of the supported pins.
* Access: Index
*/
MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
/* reg_mtpps_time_stamp
* When pin_mode = pps_in, the latched device time when it was triggered from
* the external GPIO pin.
* When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
* time to generate next output signal.
* Time is in units of device clock.
* Access: RW
*/
MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
static inline void
mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
{
MLXSW_REG_ZERO(mtpps, payload);
mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
mlxsw_reg_mtpps_pin_mode_set(payload,
MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
mlxsw_reg_mtpps_enable_set(payload, true);
mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
}
/* MTUTC - Management UTC Register
* -------------------------------
* Configures the HW UTC counter.
@ -10149,6 +10206,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(mgir),
MLXSW_REG(mrsr),
MLXSW_REG(mlcr),
MLXSW_REG(mtpps),
MLXSW_REG(mtutc),
MLXSW_REG(mpsc),
MLXSW_REG(mcqi),