unicore32 core architecture: mm related: consistent device DMA handling
This patch implements consistent device DMA handling of memory management. DMA device operations are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
GuanXuetao
parent
56372b0b2f
commit
10c9c10c31
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/*
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* linux/arch/unicore32/include/asm/cacheflush.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_CACHEFLUSH_H__
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#define __UNICORE_CACHEFLUSH_H__
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#include <linux/mm.h>
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#include <asm/shmparam.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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/*
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* This flag is used to indicate that the page pointed to by a pte is clean
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* and does not require cleaning before returning it to the user.
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*/
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#define PG_dcache_clean PG_arch_1
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/*
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* MM Cache Management
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* ===================
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*
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* The arch/unicore32/mm/cache.S files implement these methods.
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*
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* Start addresses are inclusive and end addresses are exclusive;
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* start addresses should be rounded down, end addresses up.
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*
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* See Documentation/cachetlb.txt for more information.
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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* Currently only needed for cache-v6.S and cache-v7.S, see
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* __flush_icache_all for the generic implementation.
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*
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* flush_kern_all()
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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* flush_user_all()
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_user_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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* - start - user start address (inclusive, page aligned)
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* - end - user end address (exclusive, page aligned)
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* - flags - vma->vm_flags field
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*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* flush_kern_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*
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* DMA Cache Coherency
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* ===================
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*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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* - start - virtual start address
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* - end - virtual end address
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*/
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extern void __cpuc_flush_icache_all(void);
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extern void __cpuc_flush_kern_all(void);
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extern void __cpuc_flush_user_all(void);
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extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
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extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
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extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
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extern void __cpuc_flush_dcache_area(void *, size_t);
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extern void __cpuc_flush_kern_dcache_area(void *addr, size_t size);
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/*
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* These are private to the dma-mapping API. Do not use directly.
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* Their sole purpose is to ensure that data held in the cache
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* is visible to DMA, or data written by DMA to system memory is
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* visible to the CPU.
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*/
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extern void __cpuc_dma_clean_range(unsigned long, unsigned long);
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extern void __cpuc_dma_flush_range(unsigned long, unsigned long);
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*/
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extern void copy_to_user_page(struct vm_area_struct *, struct page *,
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unsigned long, void *, const void *, unsigned long);
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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} while (0)
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/*
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* Convert calls to our calling convention.
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*/
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/* Invalidate I-cache */
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static inline void __flush_icache_all(void)
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{
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asm("movc p0.c5, %0, #20;\n"
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"nop; nop; nop; nop; nop; nop; nop; nop\n"
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:
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: "r" (0));
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}
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#define flush_cache_all() __cpuc_flush_kern_all()
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extern void flush_cache_mm(struct mm_struct *mm);
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extern void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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extern void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long pfn);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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/*
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* flush_cache_user_range is used when we want to ensure that the
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* Harvard caches are synchronised for the user space address range.
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* This is used for the UniCore private sys_cacheflush system call.
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*/
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#define flush_cache_user_range(vma, start, end) \
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__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
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/*
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* Perform necessary cache operations to ensure that data previously
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* stored within this range of addresses can be executed by the CPU.
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*/
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#define flush_icache_range(s, e) __cpuc_coherent_kern_range(s, e)
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/*
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* Perform necessary cache operations to ensure that the TLB will
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* see data written in the specified area.
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*/
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#define clean_dcache_area(start, size) cpu_dcache_clean_area(start, size)
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/*
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* flush_dcache_page is used when the kernel has written to the page
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* cache page at virtual address page->virtual.
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*
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* If this page isn't mapped (ie, page_mapping == NULL), or it might
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* have userspace mappings, then we _must_ always clean + invalidate
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* the dcache entries associated with the kernel mapping.
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*
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* Otherwise we can defer the operation, and clean the cache when we are
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* about to change to user space. This is the same method as used on SPARC64.
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* See update_mmu_cache for the user space part.
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*/
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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#define flush_dcache_mmap_lock(mapping) \
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spin_lock_irq(&(mapping)->tree_lock)
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#define flush_dcache_mmap_unlock(mapping) \
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spin_unlock_irq(&(mapping)->tree_lock)
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#define flush_icache_user_range(vma, page, addr, len) \
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flush_dcache_page(page)
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/*
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* We don't appear to need to do anything here. In fact, if we did, we'd
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* duplicate cache flushing elsewhere performed by flush_dcache_page().
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*/
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#define flush_icache_page(vma, page) do { } while (0)
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
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* caches, since the direct-mappings of these pages may contain cached
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* data, we need to do a full cache flush to ensure that writebacks
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* don't corrupt data placed into these pages via the new mappings.
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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}
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#endif
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@ -0,0 +1,124 @@
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/*
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* linux/arch/unicore32/include/asm/dma-mapping.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_DMA_MAPPING_H__
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#define __UNICORE_DMA_MAPPING_H__
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#ifdef __KERNEL__
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#include <linux/mm_types.h>
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#include <linux/scatterlist.h>
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#include <linux/swiotlb.h>
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#include <asm-generic/dma-coherent.h>
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#include <asm/memory.h>
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#include <asm/cacheflush.h>
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extern struct dma_map_ops swiotlb_dma_map_ops;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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return &swiotlb_dma_map_ops;
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}
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static inline int dma_supported(struct device *dev, u64 mask)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (unlikely(dma_ops == NULL))
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return 0;
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return dma_ops->dma_supported(dev, mask);
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}
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (dma_ops->mapping_error)
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return dma_ops->mapping_error(dev, dma_addr);
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return 0;
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}
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#include <asm-generic/dma-mapping-common.h>
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (dev && dev->dma_mask)
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return addr + size - 1 <= *dev->dma_mask;
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return 1;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr;
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr;
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}
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static inline void dma_mark_clean(void *addr, size_t size) {}
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static inline int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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return -EIO;
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*dev->dma_mask = dma_mask;
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return 0;
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}
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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struct dma_map_ops *dma_ops = get_dma_ops(dev);
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dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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static inline void dma_cache_sync(struct device *dev, void *vaddr,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long start = (unsigned long)vaddr;
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unsigned long end = start + size;
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switch (direction) {
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case DMA_NONE:
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BUG();
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL: /* writeback and invalidate */
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__cpuc_dma_flush_range(start, end);
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break;
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case DMA_TO_DEVICE: /* writeback only */
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__cpuc_dma_clean_range(start, end);
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break;
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}
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}
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#endif /* __KERNEL__ */
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#endif
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@ -0,0 +1,23 @@
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/*
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* linux/arch/unicore32/include/asm/dma.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_DMA_H__
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#define __UNICORE_DMA_H__
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#include <asm/memory.h>
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#include <asm-generic/dma.h>
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#endif
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#endif /* __UNICORE_DMA_H__ */
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@ -0,0 +1,195 @@
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/*
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* linux/arch/unicore32/include/asm/tlbflush.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_TLBFLUSH_H__
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#define __UNICORE_TLBFLUSH_H__
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long,
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struct vm_area_struct *);
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extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
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/*
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* TLB Management
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* ==============
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*
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* The arch/unicore/mm/tlb-*.S files implement these methods.
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*
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* The TLB specific code is expected to perform whatever tests it
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* needs to determine if it should invalidate the TLB for each
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* call. Start addresses are inclusive and end addresses are
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* exclusive; it is safe to round these addresses down.
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*
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* flush_tlb_all()
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*
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* Invalidate the entire TLB.
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*
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* flush_tlb_mm(mm)
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*
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* Invalidate all TLB entries in a particular address
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* space.
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* - mm - mm_struct describing address space
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*
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* flush_tlb_range(mm,start,end)
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*
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* Invalidate a range of TLB entries in the specified
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* address space.
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* - mm - mm_struct describing address space
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*
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* flush_tlb_page(vaddr,vma)
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*
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* Invalidate the specified page in the specified address range.
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* - vaddr - virtual address (may not be aligned)
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* - vma - vma_struct describing address range
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*
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* flush_kern_tlb_page(kaddr)
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*
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* Invalidate the TLB entry for the specified page. The address
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* will be in the kernels virtual memory space. Current uses
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* only require the D-TLB to be invalidated.
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* - kaddr - Kernel virtual memory address
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*/
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static inline void local_flush_tlb_all(void)
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{
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const int zero = 0;
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (zero) : "cc");
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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const int zero = 0;
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if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
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/* TLB invalidate all */
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asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (zero) : "cc");
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}
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put_cpu();
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}
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static inline void
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local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
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/* iTLB invalidate page */
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asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (uaddr & PAGE_MASK) : "cc");
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/* dTLB invalidate page */
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asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop"
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: : "r" (uaddr & PAGE_MASK) : "cc");
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#else
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/* TLB invalidate all */
|
||||
asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (uaddr & PAGE_MASK) : "cc");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
|
||||
{
|
||||
#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
|
||||
/* iTLB invalidate page */
|
||||
asm("movc p0.c6, %0, #5; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (kaddr & PAGE_MASK) : "cc");
|
||||
/* dTLB invalidate page */
|
||||
asm("movc p0.c6, %0, #3; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (kaddr & PAGE_MASK) : "cc");
|
||||
#else
|
||||
/* TLB invalidate all */
|
||||
asm("movc p0.c6, %0, #6; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (kaddr & PAGE_MASK) : "cc");
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* flush_pmd_entry
|
||||
*
|
||||
* Flush a PMD entry (word aligned, or double-word aligned) to
|
||||
* RAM if the TLB for the CPU we are running on requires this.
|
||||
* This is typically used when we are creating PMD entries.
|
||||
*
|
||||
* clean_pmd_entry
|
||||
*
|
||||
* Clean (but don't drain the write buffer) if the CPU requires
|
||||
* these operations. This is typically used when we are removing
|
||||
* PMD entries.
|
||||
*/
|
||||
static inline void flush_pmd_entry(pmd_t *pmd)
|
||||
{
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
/* flush dcache line, see dcacheline_flush in proc-macros.S */
|
||||
asm("mov r1, %0 << #20\n"
|
||||
"ldw r2, =_stext\n"
|
||||
"add r2, r2, r1 >> #20\n"
|
||||
"ldw r1, [r2+], #0x0000\n"
|
||||
"ldw r1, [r2+], #0x1000\n"
|
||||
"ldw r1, [r2+], #0x2000\n"
|
||||
"ldw r1, [r2+], #0x3000\n"
|
||||
: : "r" (pmd) : "r1", "r2");
|
||||
#else
|
||||
/* flush dcache all */
|
||||
asm("movc p0.c5, %0, #14; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (pmd) : "cc");
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void clean_pmd_entry(pmd_t *pmd)
|
||||
{
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
/* clean dcache line */
|
||||
asm("movc p0.c5, %0, #11; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (__pa(pmd) & ~(L1_CACHE_BYTES - 1)) : "cc");
|
||||
#else
|
||||
/* clean dcache all */
|
||||
asm("movc p0.c5, %0, #10; nop; nop; nop; nop; nop; nop; nop; nop"
|
||||
: : "r" (pmd) : "cc");
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert calls to our calling convention.
|
||||
*/
|
||||
#define local_flush_tlb_range(vma, start, end) \
|
||||
__cpu_flush_user_tlb_range(start, end, vma)
|
||||
#define local_flush_tlb_kernel_range(s, e) \
|
||||
__cpu_flush_kern_tlb_range(s, e)
|
||||
|
||||
#define flush_tlb_all local_flush_tlb_all
|
||||
#define flush_tlb_mm local_flush_tlb_mm
|
||||
#define flush_tlb_page local_flush_tlb_page
|
||||
#define flush_tlb_kernel_page local_flush_tlb_kernel_page
|
||||
#define flush_tlb_range local_flush_tlb_range
|
||||
#define flush_tlb_kernel_range local_flush_tlb_kernel_range
|
||||
|
||||
/*
|
||||
* if PG_dcache_clean is not set for the page, we need to ensure that any
|
||||
* cache entries for the kernels virtual memory range are written
|
||||
* back to the page.
|
||||
*/
|
||||
extern void update_mmu_cache(struct vm_area_struct *vma,
|
||||
unsigned long addr, pte_t *ptep);
|
||||
|
||||
extern void do_bad_area(unsigned long addr, unsigned int fsr,
|
||||
struct pt_regs *regs);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* linux/arch/unicore32/include/mach/dma.h
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __MACH_PUV3_DMA_H__
|
||||
#define __MACH_PUV3_DMA_H__
|
||||
|
||||
/*
|
||||
* The PKUnity has six internal DMA channels.
|
||||
*/
|
||||
#define MAX_DMA_CHANNELS 6
|
||||
|
||||
typedef enum {
|
||||
DMA_PRIO_HIGH = 0,
|
||||
DMA_PRIO_MEDIUM = 1,
|
||||
DMA_PRIO_LOW = 2
|
||||
} puv3_dma_prio;
|
||||
|
||||
/*
|
||||
* DMA registration
|
||||
*/
|
||||
|
||||
extern int puv3_request_dma(char *name,
|
||||
puv3_dma_prio prio,
|
||||
void (*irq_handler)(int, void *),
|
||||
void (*err_handler)(int, void *),
|
||||
void *data);
|
||||
|
||||
extern void puv3_free_dma(int dma_ch);
|
||||
|
||||
#define puv3_stop_dma(ch) (DMAC_CONFIG(ch) &= ~DMAC_CONFIG_EN)
|
||||
#define puv3_resume_dma(ch) (DMAC_CONFIG(ch) |= DMAC_CONFIG_EN)
|
||||
|
||||
#endif /* __MACH_PUV3_DMA_H__ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* linux/arch/unicore32/kernel/dma.c
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
|
||||
* Copyright (C) 2001-2010 Guan Xuetao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
struct dma_channel {
|
||||
char *name;
|
||||
puv3_dma_prio prio;
|
||||
void (*irq_handler)(int, void *);
|
||||
void (*err_handler)(int, void *);
|
||||
void *data;
|
||||
};
|
||||
|
||||
static struct dma_channel dma_channels[MAX_DMA_CHANNELS];
|
||||
|
||||
int puv3_request_dma(char *name, puv3_dma_prio prio,
|
||||
void (*irq_handler)(int, void *),
|
||||
void (*err_handler)(int, void *),
|
||||
void *data)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i, found = 0;
|
||||
|
||||
/* basic sanity checks */
|
||||
if (!name)
|
||||
return -EINVAL;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
do {
|
||||
/* try grabbing a DMA channel with the requested priority */
|
||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
||||
if ((dma_channels[i].prio == prio) &&
|
||||
!dma_channels[i].name) {
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* if requested prio group is full, try a hier priority */
|
||||
} while (!found && prio--);
|
||||
|
||||
if (found) {
|
||||
dma_channels[i].name = name;
|
||||
dma_channels[i].irq_handler = irq_handler;
|
||||
dma_channels[i].err_handler = err_handler;
|
||||
dma_channels[i].data = data;
|
||||
} else {
|
||||
printk(KERN_WARNING "No more available DMA channels for %s\n",
|
||||
name);
|
||||
i = -ENODEV;
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
return i;
|
||||
}
|
||||
EXPORT_SYMBOL(puv3_request_dma);
|
||||
|
||||
void puv3_free_dma(int dma_ch)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!dma_channels[dma_ch].name) {
|
||||
printk(KERN_CRIT
|
||||
"%s: trying to free channel %d which is already freed\n",
|
||||
__func__, dma_ch);
|
||||
return;
|
||||
}
|
||||
|
||||
local_irq_save(flags);
|
||||
dma_channels[dma_ch].name = NULL;
|
||||
dma_channels[dma_ch].err_handler = NULL;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(puv3_free_dma);
|
||||
|
||||
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
int i, dint = DMAC_ITCSR;
|
||||
|
||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
||||
if (dint & DMAC_CHANNEL(i)) {
|
||||
struct dma_channel *channel = &dma_channels[i];
|
||||
|
||||
/* Clear TC interrupt of channel i */
|
||||
DMAC_ITCCR = DMAC_CHANNEL(i);
|
||||
DMAC_ITCCR = 0;
|
||||
|
||||
if (channel->name && channel->irq_handler) {
|
||||
channel->irq_handler(i, channel->data);
|
||||
} else {
|
||||
/*
|
||||
* IRQ for an unregistered DMA channel:
|
||||
* let's clear the interrupts and disable it.
|
||||
*/
|
||||
printk(KERN_WARNING "spurious IRQ for"
|
||||
" DMA channel %d\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t dma_err_handler(int irq, void *dev_id)
|
||||
{
|
||||
int i, dint = DMAC_IESR;
|
||||
|
||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
||||
if (dint & DMAC_CHANNEL(i)) {
|
||||
struct dma_channel *channel = &dma_channels[i];
|
||||
|
||||
/* Clear Err interrupt of channel i */
|
||||
DMAC_IECR = DMAC_CHANNEL(i);
|
||||
DMAC_IECR = 0;
|
||||
|
||||
if (channel->name && channel->err_handler) {
|
||||
channel->err_handler(i, channel->data);
|
||||
} else {
|
||||
/*
|
||||
* IRQ for an unregistered DMA channel:
|
||||
* let's clear the interrupts and disable it.
|
||||
*/
|
||||
printk(KERN_WARNING "spurious IRQ for"
|
||||
" DMA channel %d\n", i);
|
||||
}
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int __init puv3_init_dma(void)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
/* dma channel priorities on v8 processors:
|
||||
* ch 0 - 1 <--> (0) DMA_PRIO_HIGH
|
||||
* ch 2 - 3 <--> (1) DMA_PRIO_MEDIUM
|
||||
* ch 4 - 5 <--> (2) DMA_PRIO_LOW
|
||||
*/
|
||||
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
||||
puv3_stop_dma(i);
|
||||
dma_channels[i].name = NULL;
|
||||
dma_channels[i].prio = min((i & 0x7) >> 1, DMA_PRIO_LOW);
|
||||
}
|
||||
|
||||
ret = request_irq(IRQ_DMA, dma_irq_handler, 0, "DMA", NULL);
|
||||
if (ret) {
|
||||
printk(KERN_CRIT "Can't register IRQ for DMA\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = request_irq(IRQ_DMAERR, dma_err_handler, 0, "DMAERR", NULL);
|
||||
if (ret) {
|
||||
printk(KERN_CRIT "Can't register IRQ for DMAERR\n");
|
||||
free_irq(IRQ_DMA, "DMA");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
postcore_initcall(puv3_init_dma);
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
/*
|
||||
* linux/arch/unicore32/mm/cache-ucv2.S
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This is the "shell" of the UniCore-v2 processor support.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#include "proc-macros.S"
|
||||
|
||||
/*
|
||||
* __cpuc_flush_icache_all()
|
||||
* __cpuc_flush_kern_all()
|
||||
* __cpuc_flush_user_all()
|
||||
*
|
||||
* Flush the entire cache.
|
||||
*/
|
||||
ENTRY(__cpuc_flush_icache_all)
|
||||
/*FALLTHROUGH*/
|
||||
ENTRY(__cpuc_flush_kern_all)
|
||||
/*FALLTHROUGH*/
|
||||
ENTRY(__cpuc_flush_user_all)
|
||||
mov r0, #0
|
||||
movc p0.c5, r0, #14 @ Dcache flush all
|
||||
nop8
|
||||
|
||||
mov r0, #0
|
||||
movc p0.c5, r0, #20 @ Icache invalidate all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpuc_flush_user_range(start, end, flags)
|
||||
*
|
||||
* Flush a range of TLB entries in the specified address space.
|
||||
*
|
||||
* - start - start address (may not be aligned)
|
||||
* - end - end address (exclusive, may not be aligned)
|
||||
* - flags - vm_area_struct flags describing address space
|
||||
*/
|
||||
ENTRY(__cpuc_flush_user_range)
|
||||
cxor.a r2, #0
|
||||
beq __cpuc_dma_flush_range
|
||||
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
|
||||
sub r1, r1, r0
|
||||
csub.a r1, #MAX_AREA_SIZE
|
||||
bsg 2f
|
||||
|
||||
andn r1, r1, #CACHE_LINESIZE - 1
|
||||
add r1, r1, #CACHE_LINESIZE
|
||||
|
||||
101: dcacheline_flush r0, r11, r12
|
||||
|
||||
add r0, r0, #CACHE_LINESIZE
|
||||
sub.a r1, r1, #CACHE_LINESIZE
|
||||
bns 101b
|
||||
b 3f
|
||||
#endif
|
||||
2: mov ip, #0
|
||||
movc p0.c5, ip, #14 @ Dcache flush all
|
||||
nop8
|
||||
|
||||
3: mov ip, #0
|
||||
movc p0.c5, ip, #20 @ Icache invalidate all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpuc_coherent_kern_range(start,end)
|
||||
* __cpuc_coherent_user_range(start,end)
|
||||
*
|
||||
* Ensure that the I and D caches are coherent within specified
|
||||
* region. This is typically used when code has been written to
|
||||
* a memory region, and will be executed.
|
||||
*
|
||||
* - start - virtual start address of region
|
||||
* - end - virtual end address of region
|
||||
*/
|
||||
ENTRY(__cpuc_coherent_kern_range)
|
||||
/* FALLTHROUGH */
|
||||
ENTRY(__cpuc_coherent_user_range)
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
andn r0, r0, #CACHE_LINESIZE - 1 @ Safety check
|
||||
sub r1, r1, r0
|
||||
csub.a r1, #MAX_AREA_SIZE
|
||||
bsg 2f
|
||||
|
||||
andn r1, r1, #CACHE_LINESIZE - 1
|
||||
add r1, r1, #CACHE_LINESIZE
|
||||
|
||||
@ r0 va2pa r10
|
||||
mov r9, #PAGE_SZ
|
||||
sub r9, r9, #1 @ PAGE_MASK
|
||||
101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
|
||||
b 103f
|
||||
102: cand.a r0, r9
|
||||
beq 101b
|
||||
|
||||
103: movc p0.c5, r10, #11 @ Dcache clean line of R10
|
||||
nop8
|
||||
|
||||
add r0, r0, #CACHE_LINESIZE
|
||||
add r10, r10, #CACHE_LINESIZE
|
||||
sub.a r1, r1, #CACHE_LINESIZE
|
||||
bns 102b
|
||||
b 3f
|
||||
#endif
|
||||
2: mov ip, #0
|
||||
movc p0.c5, ip, #10 @ Dcache clean all
|
||||
nop8
|
||||
|
||||
3: mov ip, #0
|
||||
movc p0.c5, ip, #20 @ Icache invalidate all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpuc_flush_kern_dcache_area(void *addr, size_t size)
|
||||
*
|
||||
* - addr - kernel address
|
||||
* - size - region size
|
||||
*/
|
||||
ENTRY(__cpuc_flush_kern_dcache_area)
|
||||
mov ip, #0
|
||||
movc p0.c5, ip, #14 @ Dcache flush all
|
||||
nop8
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpuc_dma_clean_range(start,end)
|
||||
* - start - virtual start address of region
|
||||
* - end - virtual end address of region
|
||||
*/
|
||||
ENTRY(__cpuc_dma_clean_range)
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
andn r0, r0, #CACHE_LINESIZE - 1
|
||||
sub r1, r1, r0
|
||||
andn r1, r1, #CACHE_LINESIZE - 1
|
||||
add r1, r1, #CACHE_LINESIZE
|
||||
|
||||
csub.a r1, #MAX_AREA_SIZE
|
||||
bsg 2f
|
||||
|
||||
@ r0 va2pa r10
|
||||
mov r9, #PAGE_SZ
|
||||
sub r9, r9, #1 @ PAGE_MASK
|
||||
101: va2pa r0, r10, r11, r12, r13, 2f @ r10 is PA
|
||||
b 1f
|
||||
102: cand.a r0, r9
|
||||
beq 101b
|
||||
|
||||
1: movc p0.c5, r10, #11 @ Dcache clean line of R10
|
||||
nop8
|
||||
add r0, r0, #CACHE_LINESIZE
|
||||
add r10, r10, #CACHE_LINESIZE
|
||||
sub.a r1, r1, #CACHE_LINESIZE
|
||||
bns 102b
|
||||
mov pc, lr
|
||||
#endif
|
||||
2: mov ip, #0
|
||||
movc p0.c5, ip, #10 @ Dcache clean all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpuc_dma_inv_range(start,end)
|
||||
* __cpuc_dma_flush_range(start,end)
|
||||
* - start - virtual start address of region
|
||||
* - end - virtual end address of region
|
||||
*/
|
||||
__cpuc_dma_inv_range:
|
||||
/* FALLTHROUGH */
|
||||
ENTRY(__cpuc_dma_flush_range)
|
||||
#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
|
||||
andn r0, r0, #CACHE_LINESIZE - 1
|
||||
sub r1, r1, r0
|
||||
andn r1, r1, #CACHE_LINESIZE - 1
|
||||
add r1, r1, #CACHE_LINESIZE
|
||||
|
||||
csub.a r1, #MAX_AREA_SIZE
|
||||
bsg 2f
|
||||
|
||||
@ r0 va2pa r10
|
||||
101: dcacheline_flush r0, r11, r12
|
||||
|
||||
add r0, r0, #CACHE_LINESIZE
|
||||
sub.a r1, r1, #CACHE_LINESIZE
|
||||
bns 101b
|
||||
mov pc, lr
|
||||
#endif
|
||||
2: mov ip, #0
|
||||
movc p0.c5, ip, #14 @ Dcache flush all
|
||||
nop8
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Contains routines needed to support swiotlb for UniCore32.
|
||||
*
|
||||
* Copyright (C) 2010 Guan Xuetao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#include <linux/pci.h>
|
||||
#include <linux/cache.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/swiotlb.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/dma.h>
|
||||
|
||||
struct dma_map_ops swiotlb_dma_map_ops = {
|
||||
.alloc_coherent = swiotlb_alloc_coherent,
|
||||
.free_coherent = swiotlb_free_coherent,
|
||||
.map_sg = swiotlb_map_sg_attrs,
|
||||
.unmap_sg = swiotlb_unmap_sg_attrs,
|
||||
.dma_supported = swiotlb_dma_supported,
|
||||
.map_page = swiotlb_map_page,
|
||||
.unmap_page = swiotlb_unmap_page,
|
||||
.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
|
||||
.sync_single_for_device = swiotlb_sync_single_for_device,
|
||||
.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
|
||||
.sync_sg_for_device = swiotlb_sync_sg_for_device,
|
||||
.mapping_error = swiotlb_dma_mapping_error,
|
||||
};
|
||||
EXPORT_SYMBOL(swiotlb_dma_map_ops);
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* linux/arch/unicore32/mm/flush.c
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pagemap.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
void flush_cache_mm(struct mm_struct *mm)
|
||||
{
|
||||
}
|
||||
|
||||
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
if (vma->vm_flags & VM_EXEC)
|
||||
__flush_icache_all();
|
||||
}
|
||||
|
||||
void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr,
|
||||
unsigned long pfn)
|
||||
{
|
||||
}
|
||||
|
||||
static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long uaddr, void *kaddr, unsigned long len)
|
||||
{
|
||||
/* VIPT non-aliasing D-cache */
|
||||
if (vma->vm_flags & VM_EXEC) {
|
||||
unsigned long addr = (unsigned long)kaddr;
|
||||
|
||||
__cpuc_coherent_kern_range(addr, addr + len);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy user data from/to a page which is mapped into a different
|
||||
* processes address space. Really, we want to allow our "user
|
||||
* space" model to handle this.
|
||||
*
|
||||
* Note that this code needs to run on the current CPU.
|
||||
*/
|
||||
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long uaddr, void *dst, const void *src,
|
||||
unsigned long len)
|
||||
{
|
||||
memcpy(dst, src, len);
|
||||
flush_ptrace_access(vma, page, uaddr, dst, len);
|
||||
}
|
||||
|
||||
void __flush_dcache_page(struct address_space *mapping, struct page *page)
|
||||
{
|
||||
/*
|
||||
* Writeback any data associated with the kernel mapping of this
|
||||
* page. This ensures that data in the physical page is mutually
|
||||
* coherent with the kernels mapping.
|
||||
*/
|
||||
__cpuc_flush_kern_dcache_area(page_address(page), PAGE_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure cache coherency between kernel mapping and userspace mapping
|
||||
* of this page.
|
||||
*/
|
||||
void flush_dcache_page(struct page *page)
|
||||
{
|
||||
struct address_space *mapping;
|
||||
|
||||
/*
|
||||
* The zero page is never written to, so never has any dirty
|
||||
* cache lines, and therefore never needs to be flushed.
|
||||
*/
|
||||
if (page == ZERO_PAGE(0))
|
||||
return;
|
||||
|
||||
mapping = page_mapping(page);
|
||||
|
||||
if (mapping && !mapping_mapped(mapping))
|
||||
clear_bit(PG_dcache_clean, &page->flags);
|
||||
else {
|
||||
__flush_dcache_page(mapping, page);
|
||||
if (mapping)
|
||||
__flush_icache_all();
|
||||
set_bit(PG_dcache_clean, &page->flags);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(flush_dcache_page);
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* linux/arch/unicore32/mm/tlb-ucv2.S
|
||||
*
|
||||
* Code specific to PKUnity SoC and UniCore ISA
|
||||
*
|
||||
* Copyright (C) 2001-2010 GUAN Xue-tao
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include "proc-macros.S"
|
||||
|
||||
/*
|
||||
* __cpu_flush_user_tlb_range(start, end, vma)
|
||||
*
|
||||
* Invalidate a range of TLB entries in the specified address space.
|
||||
*
|
||||
* - start - start address (may not be aligned)
|
||||
* - end - end address (exclusive, may not be aligned)
|
||||
* - vma - vma_struct describing address range
|
||||
*/
|
||||
ENTRY(__cpu_flush_user_tlb_range)
|
||||
#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
|
||||
mov r0, r0 >> #PAGE_SHIFT @ align address
|
||||
mov r0, r0 << #PAGE_SHIFT
|
||||
vma_vm_flags r2, r2 @ get vma->vm_flags
|
||||
1:
|
||||
movc p0.c6, r0, #3
|
||||
nop8
|
||||
|
||||
cand.a r2, #VM_EXEC @ Executable area ?
|
||||
beq 2f
|
||||
|
||||
movc p0.c6, r0, #5
|
||||
nop8
|
||||
2:
|
||||
add r0, r0, #PAGE_SZ
|
||||
csub.a r0, r1
|
||||
beb 1b
|
||||
#else
|
||||
movc p0.c6, r0, #2
|
||||
nop8
|
||||
|
||||
cand.a r2, #VM_EXEC @ Executable area ?
|
||||
beq 2f
|
||||
|
||||
movc p0.c6, r0, #4
|
||||
nop8
|
||||
2:
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* __cpu_flush_kern_tlb_range(start,end)
|
||||
*
|
||||
* Invalidate a range of kernel TLB entries
|
||||
*
|
||||
* - start - start address (may not be aligned)
|
||||
* - end - end address (exclusive, may not be aligned)
|
||||
*/
|
||||
ENTRY(__cpu_flush_kern_tlb_range)
|
||||
#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
|
||||
mov r0, r0 >> #PAGE_SHIFT @ align address
|
||||
mov r0, r0 << #PAGE_SHIFT
|
||||
1:
|
||||
movc p0.c6, r0, #3
|
||||
nop8
|
||||
|
||||
movc p0.c6, r0, #5
|
||||
nop8
|
||||
|
||||
add r0, r0, #PAGE_SZ
|
||||
csub.a r0, r1
|
||||
beb 1b
|
||||
#else
|
||||
movc p0.c6, r0, #2
|
||||
nop8
|
||||
|
||||
movc p0.c6, r0, #4
|
||||
nop8
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
Loading…
Reference in New Issue