ibm_newemac: PowerPC 440EP/440GR EMAC PHY clock workaround
This patch adds ibm_newemac PHY clock workaround for 440EP/440GR EMAC attached to a PHY which doesn't generate RX clock if there is no link. The code is based on the previous ibm_emac driver stuff. The 440EP/440GR allows controlling each EMAC clock separately as opposed to global clock selection for 440GX. BenH: Made that #ifdef CONFIG_PPC_DCR_NATIVE for now as dcri_* stuff doesn't exist for MMIO type DCRs like Cell. Some future rework & improvements of the DCR infrastructure will make that cleaner but for now, this makes it work. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -129,10 +129,35 @@ static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
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static inline void emac_report_timeout_error(struct emac_instance *dev,
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const char *error)
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{
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if (net_ratelimit())
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if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
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EMAC_FTR_440EP_PHY_CLK_FIX))
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DBG(dev, "%s" NL, error);
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else if (net_ratelimit())
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printk(KERN_ERR "%s: %s\n", dev->ndev->name, error);
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}
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/* EMAC PHY clock workaround:
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* 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
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* which allows controlling each EMAC clock
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*/
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static inline void emac_rx_clk_tx(struct emac_instance *dev)
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{
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_MFR,
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0, SDR0_MFR_ECS >> dev->cell_index);
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#endif
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}
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static inline void emac_rx_clk_default(struct emac_instance *dev)
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{
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_MFR,
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SDR0_MFR_ECS >> dev->cell_index, 0);
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#endif
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}
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/* PHY polling intervals */
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#define PHY_POLL_LINK_ON HZ
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#define PHY_POLL_LINK_OFF (HZ / 5)
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@ -1099,9 +1124,11 @@ static int emac_open(struct net_device *ndev)
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int link_poll_interval;
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if (dev->phy.def->ops->poll_link(&dev->phy)) {
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dev->phy.def->ops->read_link(&dev->phy);
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emac_rx_clk_default(dev);
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netif_carrier_on(dev->ndev);
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link_poll_interval = PHY_POLL_LINK_ON;
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} else {
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emac_rx_clk_tx(dev);
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netif_carrier_off(dev->ndev);
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link_poll_interval = PHY_POLL_LINK_OFF;
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}
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@ -1179,6 +1206,7 @@ static void emac_link_timer(struct work_struct *work)
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if (dev->phy.def->ops->poll_link(&dev->phy)) {
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if (!netif_carrier_ok(dev->ndev)) {
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emac_rx_clk_default(dev);
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/* Get new link parameters */
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dev->phy.def->ops->read_link(&dev->phy);
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@ -1191,6 +1219,7 @@ static void emac_link_timer(struct work_struct *work)
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link_poll_interval = PHY_POLL_LINK_ON;
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} else {
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if (netif_carrier_ok(dev->ndev)) {
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emac_rx_clk_tx(dev);
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netif_carrier_off(dev->ndev);
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netif_tx_disable(dev->ndev);
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emac_reinitialize(dev);
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@ -2339,6 +2368,14 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
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#endif
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/* PHY clock workaround */
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emac_rx_clk_tx(dev);
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/* Enable internal clock source on 440GX*/
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
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#endif
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/* Configure EMAC with defaults so we can at least use MDIO
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* This is needed mostly for 440GX
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@ -2507,6 +2544,10 @@ static int __devinit emac_init_config(struct emac_instance *dev)
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dev->features |= EMAC_FTR_EMAC4;
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if (of_device_is_compatible(np, "ibm,emac-440gx"))
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dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
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} else {
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if (of_device_is_compatible(np, "ibm,emac-440ep") ||
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of_device_is_compatible(np, "ibm,emac-440gr"))
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dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
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}
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/* Fixup some feature bits based on the device tree */
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@ -305,6 +305,10 @@ struct emac_instance {
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* Set if we need phy clock workaround for 440gx
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*/
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#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
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/*
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* Set if we need phy clock workaround for 440ep or 440gr
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*/
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#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
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/* Right now, we don't quite handle the always/possible masks on the
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@ -328,7 +332,7 @@ enum {
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#ifdef CONFIG_IBM_NEW_EMAC_RGMII
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EMAC_FTR_HAS_RGMII |
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#endif
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0,
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EMAC_FTR_440EP_PHY_CLK_FIX,
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};
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static inline int emac_has_feature(struct emac_instance *dev,
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