Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/ptrace: Remove BUG_ON when full register set not available powerpc: Factoring mpic cpu id fetching into a function powerpc: Make MPIC honor the "pic-no-reset" device tree property powerpc: Document the Open PIC device tree binding powerpc/pci: Fix crash in PCI code on ppc64 when matching device nodeshifive-unleashed-5.1
Linus Torvalds
commit
111f4268bd
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@ -0,0 +1,98 @@
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* Open PIC Binding
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This binding specifies what properties must be available in the device tree
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representation of an Open PIC compliant interrupt controller. This binding is
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based on the binding defined for Open PIC in [1] and is a superset of that
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binding.
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Required properties:
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NOTE: Many of these descriptions were paraphrased here from [1] to aid
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readability.
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- compatible: Specifies the compatibility list for the PIC. The type
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shall be <string> and the value shall include "open-pic".
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- reg: Specifies the base physical address(s) and size(s) of this
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PIC's addressable register space. The type shall be <prop-encoded-array>.
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- interrupt-controller: The presence of this property identifies the node
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as an Open PIC. No property value shall be defined.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 2.
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- #address-cells: Specifies the number of cells needed to encode an
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address. The type shall be <u32> and the value shall be 0. As such,
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'interrupt-map' nodes do not have to specify a parent unit address.
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Optional properties:
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- pic-no-reset: The presence of this property indicates that the PIC
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shall not be reset during runtime initialization. No property value shall
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be defined. The presence of this property also mandates that any
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initialization related to interrupt sources shall be limited to sources
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explicitly referenced in the device tree.
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* Interrupt Specifier Definition
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Interrupt specifiers consists of 2 cells encoded as
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follows:
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- <1st-cell>: The interrupt-number that identifies the interrupt source.
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- <2nd-cell>: The level-sense information, encoded as follows:
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0 = low-to-high edge triggered
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1 = active low level-sensitive
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2 = active high level-sensitive
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3 = high-to-low edge triggered
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* Examples
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Example 1:
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/*
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* An Open PIC interrupt controller
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*/
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mpic: pic@40000 {
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// This is an interrupt controller node.
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interrupt-controller;
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// No address cells so that 'interrupt-map' nodes which reference
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// this Open PIC node do not need a parent address specifier.
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#address-cells = <0>;
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// Two cells to encode interrupt sources.
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#interrupt-cells = <2>;
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// Offset address of 0x40000 and size of 0x40000.
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reg = <0x40000 0x40000>;
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// Compatible with Open PIC.
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compatible = "open-pic";
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// The PIC shall not be reset.
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pic-no-reset;
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};
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Example 2:
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/*
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* An interrupt generating device that is wired to an Open PIC.
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*/
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serial0: serial@4500 {
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// Interrupt source '42' that is active high level-sensitive.
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// Note that there are only two cells as specified in the interrupt
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// parent's '#interrupt-cells' property.
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interrupts = <42 2>;
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// The interrupt controller that this device is wired to.
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interrupt-parent = <&mpic>;
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};
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* References
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[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
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Requirements (ePAPR), Version 1.0, July 2008.
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(http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
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@ -367,6 +367,10 @@ struct mpic
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#define MPIC_SINGLE_DEST_CPU 0x00001000
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/* Enable CoreInt delivery of interrupts */
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#define MPIC_ENABLE_COREINT 0x00002000
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/* Disable resetting of the MPIC.
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* NOTE: This flag trumps MPIC_WANTS_RESET.
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*/
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#define MPIC_NO_RESET 0x00004000
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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@ -125,8 +125,10 @@ extern int ptrace_put_reg(struct task_struct *task, int regno,
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#endif /* ! __powerpc64__ */
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#define TRAP(regs) ((regs)->trap & ~0xF)
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#ifdef __powerpc64__
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#define NV_REG_POISON 0xdeadbeefdeadbeefUL
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#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
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#else
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#define NV_REG_POISON 0xdeadbeef
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#define CHECK_FULL_REGS(regs) \
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do { \
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if ((regs)->trap & 1) \
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@ -176,11 +176,14 @@ static void *is_devfn_node(struct device_node *dn, void *data)
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*/
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struct device_node *fetch_dev_dn(struct pci_dev *dev)
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{
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struct device_node *orig_dn = dev->dev.of_node;
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struct pci_controller *phb = dev->sysdata;
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struct device_node *dn;
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unsigned long searchval = (dev->bus->number << 8) | dev->devfn;
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dn = traverse_pci_devices(orig_dn, is_devfn_node, (void *)searchval);
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if (WARN_ON(!phb))
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return NULL;
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dn = traverse_pci_devices(phb->dn, is_devfn_node, (void *)searchval);
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if (dn)
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dev->dev.of_node = dn;
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return dn;
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@ -229,12 +229,16 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int ret;
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int i, ret;
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if (target->thread.regs == NULL)
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return -EIO;
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CHECK_FULL_REGS(target->thread.regs);
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if (!FULL_REGS(target->thread.regs)) {
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/* We have a partial register set. Fill 14-31 with bogus values */
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for (i = 14; i < 32; i++)
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target->thread.regs->gpr[i] = NV_REG_POISON;
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}
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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target->thread.regs,
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@ -641,11 +645,16 @@ static int gpr32_get(struct task_struct *target,
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compat_ulong_t *k = kbuf;
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compat_ulong_t __user *u = ubuf;
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compat_ulong_t reg;
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int i;
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if (target->thread.regs == NULL)
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return -EIO;
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CHECK_FULL_REGS(target->thread.regs);
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if (!FULL_REGS(target->thread.regs)) {
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/* We have a partial register set. Fill 14-31 with bogus values */
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for (i = 14; i < 32; i++)
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target->thread.regs->gpr[i] = NV_REG_POISON;
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}
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pos /= sizeof(reg);
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count /= sizeof(reg);
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@ -147,6 +147,16 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
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#endif /* CONFIG_MPIC_WEIRD */
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static inline unsigned int mpic_processor_id(struct mpic *mpic)
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{
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unsigned int cpu = 0;
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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return cpu;
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}
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/*
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* Register accessor functions
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*/
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@ -210,19 +220,14 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
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{
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unsigned int cpu = 0;
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unsigned int cpu = mpic_processor_id(mpic);
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
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}
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static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
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{
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unsigned int cpu = 0;
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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unsigned int cpu = mpic_processor_id(mpic);
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_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
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}
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@ -913,6 +918,20 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
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mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
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}
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void mpic_set_destination(unsigned int virq, unsigned int cpuid)
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{
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struct mpic *mpic = mpic_from_irq(virq);
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unsigned int src = mpic_irq_to_hw(virq);
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DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
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mpic, virq, src, cpuid);
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if (src >= mpic->irq_count)
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return;
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mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
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}
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static struct irq_chip mpic_irq_chip = {
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.irq_mask = mpic_mask_irq,
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.irq_unmask = mpic_unmask_irq,
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@ -993,6 +1012,16 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
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/* Set default irq type */
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set_irq_type(virq, IRQ_TYPE_NONE);
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/* If the MPIC was reset, then all vectors have already been
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* initialized. Otherwise, a per source lazy initialization
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* is done here.
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*/
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if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
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mpic_set_vector(virq, hw);
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mpic_set_destination(virq, mpic_processor_id(mpic));
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mpic_irq_set_priority(virq, 8);
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}
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return 0;
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}
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@ -1040,6 +1069,11 @@ static struct irq_host_ops mpic_host_ops = {
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.xlate = mpic_host_xlate,
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};
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static int mpic_reset_prohibited(struct device_node *node)
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{
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return node && of_get_property(node, "pic-no-reset", NULL);
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}
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/*
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* Exported functions
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*/
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@ -1160,7 +1194,15 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
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/* Reset */
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if (flags & MPIC_WANTS_RESET) {
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/* When using a device-node, reset requests are only honored if the MPIC
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* is allowed to reset.
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*/
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if (mpic_reset_prohibited(node))
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mpic->flags |= MPIC_NO_RESET;
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if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
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printk(KERN_DEBUG "mpic: Resetting\n");
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mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
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mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
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| MPIC_GREG_GCONF_RESET);
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@ -1320,22 +1362,21 @@ void __init mpic_init(struct mpic *mpic)
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mpic_pasemi_msi_init(mpic);
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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else
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cpu = 0;
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cpu = mpic_processor_id(mpic);
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for (i = 0; i < mpic->num_sources; i++) {
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/* start with vector = source number, and masked */
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u32 vecpri = MPIC_VECPRI_MASK | i |
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(8 << MPIC_VECPRI_PRIORITY_SHIFT);
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if (!(mpic->flags & MPIC_NO_RESET)) {
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for (i = 0; i < mpic->num_sources; i++) {
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/* start with vector = source number, and masked */
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u32 vecpri = MPIC_VECPRI_MASK | i |
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(8 << MPIC_VECPRI_PRIORITY_SHIFT);
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/* check if protected */
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if (mpic->protected && test_bit(i, mpic->protected))
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continue;
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/* init hw */
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mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
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mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
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/* check if protected */
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if (mpic->protected && test_bit(i, mpic->protected))
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continue;
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/* init hw */
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mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
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mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
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}
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}
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/* Init spurious vector */
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