x86: mce: Use safer ways to access MCE registers
Use rdmsrl_safe() when accessing MCE registers. While in theory we always 'know' which ones are safe to access from the capability bits, there's a lot of hardware variations and reality might differ from theory, as it did in this case: http://bugzilla.kernel.org/show_bug.cgi?id=14204 [ 0.010016] mce: CPU supports 5 MCE banks [ 0.011029] general protection fault: 0000 [#1] [ 0.011998] last sysfs file: [ 0.011998] Modules linked in: [ 0.011998] [ 0.011998] Pid: 0, comm: swapper Not tainted (2.6.31_router #1) HP Vectra [ 0.011998] EIP: 0060:[<c100d9b9>] EFLAGS: 00010246 CPU: 0 [ 0.011998] EIP is at mce_rdmsrl+0x19/0x60 [ 0.011998] EAX: 00000000 EBX: 00000001 ECX: 00000407 EDX: 08000000 [ 0.011998] ESI: 00000000 EDI: 8c000000 EBP: 00000405 ESP: c17d5eac So WARN_ONCE() instead of crashing the box. ( also fix a number of stylistic inconsistencies in the code. ) Note, we might still crash in wrmsrl() if we get that far, but we shouldnt if the registers are truly inaccessible. Reported-by: GNUtoo <GNUtoo@no-log.org> Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Cc: Huang Ying <ying.huang@intel.com> Cc: Andi Kleen <ak@linux.intel.com> LKML-Reference: <bug-14204-5438@http.bugzilla.kernel.org/> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -305,13 +305,25 @@ static int msr_to_offset(u32 msr)
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static u64 mce_rdmsrl(u32 msr)
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{
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u64 v;
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if (__get_cpu_var(injectm).finished) {
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int offset = msr_to_offset(msr);
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if (offset < 0)
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return 0;
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return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
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}
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rdmsrl(msr, v);
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if (rdmsrl_safe(msr, &v)) {
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WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
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/*
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* Return zero in case the access faulted. This should
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* not happen normally but can happen if the CPU does
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* something weird, or if the code is buggy.
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*/
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v = 0;
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}
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return v;
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}
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@ -319,6 +331,7 @@ static void mce_wrmsrl(u32 msr, u64 v)
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{
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if (__get_cpu_var(injectm).finished) {
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int offset = msr_to_offset(msr);
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if (offset >= 0)
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*(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
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return;
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@ -415,7 +428,7 @@ static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
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m->ip = mce_rdmsrl(rip_msr);
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Called after interrupts have been reenabled again
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* when a MCE happened during an interrupts off region
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@ -1172,6 +1185,7 @@ static int mce_banks_init(void)
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return -ENOMEM;
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for (i = 0; i < banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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b->ctl = -1ULL;
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b->init = 1;
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}
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@ -1203,6 +1217,7 @@ static int __cpuinit mce_cap_init(void)
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banks = b;
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if (!mce_banks) {
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int err = mce_banks_init();
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if (err)
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return err;
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}
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@ -1237,6 +1252,7 @@ static void mce_init(void)
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for (i = 0; i < banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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if (!b->init)
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continue;
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wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
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@ -1626,6 +1642,7 @@ static int mce_disable(void)
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for (i = 0; i < banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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if (b->init)
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wrmsrl(MSR_IA32_MCx_CTL(i), 0);
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}
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@ -1911,6 +1928,7 @@ static void mce_disable_cpu(void *h)
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cmci_clear();
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for (i = 0; i < banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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if (b->init)
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wrmsrl(MSR_IA32_MCx_CTL(i), 0);
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}
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@ -1928,6 +1946,7 @@ static void mce_reenable_cpu(void *h)
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cmci_reenable();
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for (i = 0; i < banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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if (b->init)
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wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
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}
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