ARM: vexpress/TC2: basic PM support
This is the MCPM backend for the Virtual Express A15x2 A7x3 CoreTile aka TC2. This provides cluster management for SMP secondary boot and CPU hotplug. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Pawel Moll <pawel.moll@arm.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [PM: made it drive SCC registers directly and provide base for SPC] Signed-off-by: Pawel Moll <pawel.moll@arm.com>hifive-unleashed-5.1
Nicolas Pitre
Pawel Moll
parent
ceca0e1c39
commit
11b277eabe
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@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB
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This is needed to provide CPU and cluster power management
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on RTSM implementing big.LITTLE.
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config ARCH_VEXPRESS_TC2_PM
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bool "Versatile Express TC2 power management"
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depends on MCPM
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select ARM_CCI
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help
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Support for CPU and cluster power management on Versatile Express
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with a TC2 (A15x2 A7x3) big.LITTLE core tile.
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endmenu
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@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
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obj-y := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
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obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
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obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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@ -0,0 +1,327 @@
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/*
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* arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
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*
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* Created by: Nicolas Pitre, October 2012
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* Copyright: (C) 2012-2013 Linaro Limited
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*
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* Some portions of this file were originally written by Achin Gupta
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* Copyright: (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <asm/mcpm.h>
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#include <asm/proc-fns.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <linux/arm-cci.h>
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#include "spc.h"
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/* SCC conf registers */
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#define A15_CONF 0x400
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#define A7_CONF 0x500
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#define SYS_INFO 0x700
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#define SPC_BASE 0xb00
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() after its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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#define TC2_CLUSTERS 2
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#define TC2_MAX_CPUS_PER_CLUSTER 3
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static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
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/* Keep per-cpu usage count to cope with unordered up/down requests */
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static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
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#define tc2_cluster_unused(cluster) \
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(!tc2_pm_use_count[0][cluster] && \
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!tc2_pm_use_count[1][cluster] && \
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!tc2_pm_use_count[2][cluster])
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static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
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{
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
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return -EINVAL;
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&tc2_pm_lock);
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if (tc2_cluster_unused(cluster))
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ve_spc_powerdown(cluster, false);
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tc2_pm_use_count[cpu][cluster]++;
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if (tc2_pm_use_count[cpu][cluster] == 1) {
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ve_spc_set_resume_addr(cluster, cpu,
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virt_to_phys(mcpm_entry_point));
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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} else if (tc2_pm_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_enable();
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return 0;
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}
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static void tc2_pm_power_down(void)
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{
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unsigned int mpidr, cpu, cluster;
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bool last_man = false, skip_wfi = false;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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__mcpm_cpu_going_down(cpu, cluster);
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arch_spin_lock(&tc2_pm_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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tc2_pm_use_count[cpu][cluster]--;
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if (tc2_pm_use_count[cpu][cluster] == 0) {
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ve_spc_cpu_wakeup_irq(cluster, cpu, true);
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if (tc2_cluster_unused(cluster)) {
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ve_spc_powerdown(cluster, true);
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ve_spc_global_wakeup_irq(true);
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last_man = true;
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}
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} else if (tc2_pm_use_count[cpu][cluster] == 1) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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*/
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skip_wfi = true;
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} else
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BUG();
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&tc2_pm_lock);
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if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3 \n\t"
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"isb \n\t"
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"dsb "
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: : "r" (0x400) );
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}
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/*
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* We need to disable and flush the whole (L1 and L2) cache.
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* Let's do it in the safest possible way i.e. with
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* no memory access within the following sequence
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* including the stack.
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*/
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_all \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb "
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","r11","lr","memory");
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cci_disable_port_by_cpu(mpidr);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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/*
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* If last man then undo any setup done previously.
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*/
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if (last_man) {
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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}
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arch_spin_unlock(&tc2_pm_lock);
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/*
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* We need to disable and flush only the L1 cache.
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* Let's do it in the safest possible way as above.
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*/
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_louis \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb "
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","r11","lr","memory");
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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}
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static void tc2_pm_powered_up(void)
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{
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unsigned int mpidr, cpu, cluster;
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unsigned long flags;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
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local_irq_save(flags);
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arch_spin_lock(&tc2_pm_lock);
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if (tc2_cluster_unused(cluster)) {
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ve_spc_powerdown(cluster, false);
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ve_spc_global_wakeup_irq(false);
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}
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if (!tc2_pm_use_count[cpu][cluster])
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tc2_pm_use_count[cpu][cluster] = 1;
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ve_spc_cpu_wakeup_irq(cluster, cpu, false);
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ve_spc_set_resume_addr(cluster, cpu, 0);
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arch_spin_unlock(&tc2_pm_lock);
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local_irq_restore(flags);
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}
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static const struct mcpm_platform_ops tc2_pm_power_ops = {
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.power_up = tc2_pm_power_up,
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.power_down = tc2_pm_power_down,
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.powered_up = tc2_pm_powered_up,
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};
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static bool __init tc2_pm_usage_count_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
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pr_err("%s: boot CPU is out of bound!\n", __func__);
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return false;
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}
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tc2_pm_use_count[cpu][cluster] = 1;
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return true;
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}
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile (" \n"
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" cmp r0, #1 \n"
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" bxne lr \n"
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" b cci_enable_port_for_self ");
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}
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static int __init tc2_pm_init(void)
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{
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int ret;
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void __iomem *scc;
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u32 a15_cluster_id, a7_cluster_id, sys_info;
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struct device_node *np;
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/*
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* The power management-related features are hidden behind
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* SCC registers. We need to extract runtime information like
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* cluster ids and number of CPUs really available in clusters.
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*/
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np = of_find_compatible_node(NULL, NULL,
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"arm,vexpress-scc,v2p-ca15_a7");
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scc = of_iomap(np, 0);
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if (!scc)
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return -ENODEV;
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a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
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a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
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if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
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return -EINVAL;
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sys_info = readl_relaxed(scc + SYS_INFO);
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tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
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tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
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/*
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* A subset of the SCC registers is also used to communicate
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* with the SPC (power controller). We need to be able to
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* drive it very early in the boot process to power up
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* processors, so we initialize the SPC driver here.
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*/
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ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id);
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if (ret)
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return ret;
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if (!cci_probed())
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return -ENODEV;
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if (!tc2_pm_usage_count_init())
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return -EINVAL;
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ret = mcpm_platform_register(&tc2_pm_power_ops);
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if (!ret) {
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mcpm_sync_init(tc2_pm_power_up_setup);
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pr_info("TC2 power management initialized\n");
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}
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return ret;
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}
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early_initcall(tc2_pm_init);
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