ppc440spe-adma: adds updated ppc440spe adma driver
This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>hifive-unleashed-5.1
Anatolij Gustschin
Dan Williams
parent
2e032b62c4
commit
12458ea06e
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@ -0,0 +1,93 @@
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PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
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Device nodes needed for operation of the ppc440spe-adma driver
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are specified hereby. These are I2O/DMA, DMA and XOR nodes
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for DMA engines and Memory Queue Module node. The latter is used
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by ADMA driver for configuration of RAID-6 H/W capabilities of
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the PPC440SPe. In addition to the nodes and properties described
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below, the ranges property of PLB node must specify ranges for
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DMA devices.
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i) The I2O node
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Required properties:
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- compatible : "ibm,i2o-440spe";
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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Example:
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I2O: i2o@400100000 {
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compatible = "ibm,i2o-440spe";
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reg = <0x00000004 0x00100000 0x100>;
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dcr-reg = <0x060 0x020>;
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};
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ii) The DMA node
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Required properties:
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- compatible : "ibm,dma-440spe";
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- cell-index : 1 cell, hardware index of the DMA engine
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(typically 0x0 and 0x1 for DMA0 and DMA1)
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- reg : <registers mapping>
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- dcr-reg : <DCR registers range>
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- interrupts : <interrupt mapping for DMA0/1 interrupts sources:
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2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
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and DMA Error IRQ (on UIC1). The latter is common
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for both DMA engines>.
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- interrupt-parent : needed for interrupt mapping
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Example:
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DMA0: dma0@400100100 {
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compatible = "ibm,dma-440spe";
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cell-index = <0>;
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reg = <0x00000004 0x00100100 0x100>;
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dcr-reg = <0x060 0x020>;
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interrupt-parent = <&DMA0>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <
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0 &UIC0 0x14 4
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1 &UIC1 0x16 4>;
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};
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iii) XOR Accelerator node
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Required properties:
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- compatible : "amcc,xor-accelerator";
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- reg : <registers mapping>
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- interrupts : <interrupt mapping for XOR interrupt source>
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- interrupt-parent : for interrupt mapping
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Example:
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xor-accel@400200000 {
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compatible = "amcc,xor-accelerator";
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reg = <0x00000004 0x00200000 0x400>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x1f 4>;
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};
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iv) Memory Queue Module node
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Required properties:
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- compatible : "ibm,mq-440spe";
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- dcr-reg : <DCR registers range>
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Example:
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MQ0: mq {
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compatible = "ibm,mq-440spe";
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dcr-reg = <0x040 0x020>;
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};
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@ -0,0 +1,47 @@
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/*
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* Copyright (C) 2008-2009 DENX Software Engineering.
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*
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* Author: Yuri Tikhonov <yur@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef _ASM_POWERPC_ASYNC_TX_H_
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#define _ASM_POWERPC_ASYNC_TX_H_
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#if defined(CONFIG_440SPe) || defined(CONFIG_440SP)
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extern struct dma_chan *
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ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap,
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struct page **dst_lst, int dst_cnt, struct page **src_lst,
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int src_cnt, size_t src_sz);
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#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \
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src_cnt, src_sz) \
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ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \
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src_cnt, src_sz)
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#else
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#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
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__async_tx_find_channel(dep, type)
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struct dma_chan *
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__async_tx_find_channel(struct async_submit_ctl *submit,
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enum dma_transaction_type tx_type);
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#endif
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#endif
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@ -157,4 +157,27 @@
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#define L2C_SNP_SSR_32G 0x0000f000
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#define L2C_SNP_ESR 0x00000800
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/*
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* DCR register offsets for 440SP/440SPe I2O/DMA controller.
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* The base address is configured in the device tree.
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*/
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#define DCRN_I2O0_IBAL 0x006
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#define DCRN_I2O0_IBAH 0x007
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#define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */
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/* 440SP/440SPe Software Reset DCR */
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#define DCRN_SDR0_SRST 0x0200
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#define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */
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/* 440SP/440SPe Memory Queue DCR offsets */
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#define DCRN_MQ0_XORBA 0x04
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#define DCRN_MQ0_CF2H 0x06
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#define DCRN_MQ0_CFBHL 0x0f
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#define DCRN_MQ0_BAUH 0x10
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/* HB/LL Paths Configuration Register */
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#define MQ0_CFBHL_TPLM 28
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#define MQ0_CFBHL_HBCL 23
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#define MQ0_CFBHL_POLY 15
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#endif /* __DCR_REGS_H__ */
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@ -116,6 +116,17 @@ config COH901318
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config AMCC_PPC440SPE_ADMA
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tristate "AMCC PPC440SPe ADMA support"
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depends on 440SPe || 440SP
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select DMA_ENGINE
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select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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help
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Enable support for the AMCC PPC440SPe RAID engines.
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config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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bool
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config DMA_ENGINE
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bool
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@ -11,3 +11,4 @@ obj-$(CONFIG_MX3_IPU) += ipu/
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obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
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obj-$(CONFIG_SH_DMAE) += shdma.o
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obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
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obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
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@ -0,0 +1 @@
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obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += adma.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,195 @@
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/*
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* 2006-2009 (C) DENX Software Engineering.
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*
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* Author: Yuri Tikhonov <yur@emcraft.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of
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* any kind, whether express or implied.
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*/
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#ifndef _PPC440SPE_ADMA_H
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#define _PPC440SPE_ADMA_H
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#include <linux/types.h>
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#include "dma.h"
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#include "xor.h"
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#define to_ppc440spe_adma_chan(chan) \
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container_of(chan, struct ppc440spe_adma_chan, common)
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#define to_ppc440spe_adma_device(dev) \
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container_of(dev, struct ppc440spe_adma_device, common)
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#define tx_to_ppc440spe_adma_slot(tx) \
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container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
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/* Default polynomial (for 440SP is only available) */
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#define PPC440SPE_DEFAULT_POLY 0x4d
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#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
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#define PPC440SPE_ADMA_WATCHDOG_MSEC 3
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#define PPC440SPE_ADMA_THRESHOLD 1
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#define PPC440SPE_DMA0_ID 0
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#define PPC440SPE_DMA1_ID 1
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#define PPC440SPE_XOR_ID 2
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#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
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/* this is the XOR_CBBCR width */
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#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
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#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
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#define PPC440SPE_RXOR_RUN 0
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#define MQ0_CF2H_RXOR_BS_MASK 0x1FF
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#undef ADMA_LL_DEBUG
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/**
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* struct ppc440spe_adma_device - internal representation of an ADMA device
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* @dev: device
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* @dma_reg: base for DMAx register access
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* @xor_reg: base for XOR register access
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* @i2o_reg: base for I2O register access
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* @id: HW ADMA Device selector
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* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
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* @dma_desc_pool: base of DMA descriptor region (DMA address)
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* @pool_size: size of the pool
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* @irq: DMAx or XOR irq number
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* @err_irq: DMAx error irq number
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* @common: embedded struct dma_device
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*/
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struct ppc440spe_adma_device {
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struct device *dev;
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struct dma_regs __iomem *dma_reg;
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struct xor_regs __iomem *xor_reg;
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struct i2o_regs __iomem *i2o_reg;
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int id;
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void *dma_desc_pool_virt;
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dma_addr_t dma_desc_pool;
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size_t pool_size;
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int irq;
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int err_irq;
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struct dma_device common;
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};
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/**
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* struct ppc440spe_adma_chan - internal representation of an ADMA channel
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* @lock: serializes enqueue/dequeue operations to the slot pool
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* @device: parent device
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* @chain: device chain view of the descriptors
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* @common: common dmaengine channel object members
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* @all_slots: complete domain of slots usable by the channel
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* @pending: allows batching of hardware operations
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* @completed_cookie: identifier for the most recently completed operation
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @hw_chain_inited: h/w descriptor chain initialization flag
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* @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
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* @needs_unmap: if buffers should not be unmapped upon final processing
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* @pdest_page: P destination page for async validate operation
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* @qdest_page: Q destination page for async validate operation
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* @pdest: P dma addr for async validate operation
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* @qdest: Q dma addr for async validate operation
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*/
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struct ppc440spe_adma_chan {
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spinlock_t lock;
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struct ppc440spe_adma_device *device;
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struct list_head chain;
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struct dma_chan common;
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struct list_head all_slots;
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struct ppc440spe_adma_desc_slot *last_used;
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int pending;
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dma_cookie_t completed_cookie;
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int slots_allocated;
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int hw_chain_inited;
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struct tasklet_struct irq_tasklet;
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u8 needs_unmap;
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struct page *pdest_page;
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struct page *qdest_page;
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dma_addr_t pdest;
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dma_addr_t qdest;
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};
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struct ppc440spe_rxor {
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u32 addrl;
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u32 addrh;
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int len;
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int xor_count;
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int addr_count;
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int desc_count;
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int state;
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};
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/**
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* struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
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* @phys: hardware address of the hardware descriptor chain
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* @group_head: first operation in a transaction
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* @hw_next: pointer to the next descriptor in chain
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* @async_tx: support for the async_tx api
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* @slot_node: node on the iop_adma_chan.all_slots list
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* @chain_node: node on the op_adma_chan.chain list
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* @group_list: list of slots that make up a multi-descriptor transaction
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* for example transfer lengths larger than the supported hw max
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* @unmap_len: transaction bytecount
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* @hw_desc: virtual address of the hardware descriptor chain
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* @stride: currently chained or not
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* @idx: pool index
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* @slot_cnt: total slots used in an transaction (group of operations)
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* @src_cnt: number of sources set in this descriptor
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* @dst_cnt: number of destinations set in the descriptor
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* @slots_per_op: number of slots per operation
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* @descs_per_op: number of slot per P/Q operation see comment
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* for ppc440spe_prep_dma_pqxor function
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* @flags: desc state/type
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* @reverse_flags: 1 if a corresponding rxor address uses reversed address order
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* @xor_check_result: result of zero sum
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* @crc32_result: result crc calculation
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*/
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struct ppc440spe_adma_desc_slot {
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dma_addr_t phys;
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struct ppc440spe_adma_desc_slot *group_head;
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struct ppc440spe_adma_desc_slot *hw_next;
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struct dma_async_tx_descriptor async_tx;
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struct list_head slot_node;
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struct list_head chain_node; /* node in channel ops list */
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struct list_head group_list; /* list */
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unsigned int unmap_len;
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void *hw_desc;
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u16 stride;
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u16 idx;
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u16 slot_cnt;
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u8 src_cnt;
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u8 dst_cnt;
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u8 slots_per_op;
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u8 descs_per_op;
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unsigned long flags;
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unsigned long reverse_flags[8];
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#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
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#define PPC440SPE_ZERO_P 1 /* clear P destionaion */
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#define PPC440SPE_ZERO_Q 2 /* clear Q destination */
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#define PPC440SPE_COHERENT 3 /* src/dst are coherent */
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#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
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#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
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#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
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#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
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#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
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#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
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#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
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#define PPC440SPE_DESC_PCHECK 13
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#define PPC440SPE_DESC_QCHECK 14
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#define PPC440SPE_DESC_RXOR_MSK 0x3
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struct ppc440spe_rxor rxor_cursor;
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union {
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u32 *xor_check_result;
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u32 *crc32_result;
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};
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};
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#endif /* _PPC440SPE_ADMA_H */
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@ -0,0 +1,223 @@
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/*
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* 440SPe's DMA engines support header file
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*
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* 2006-2009 (C) DENX Software Engineering.
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*
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* Author: Yuri Tikhonov <yur@emcraft.com>
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*
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* This file is licensed under the term of the GNU General Public License
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* version 2. The program licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef _PPC440SPE_DMA_H
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#define _PPC440SPE_DMA_H
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#include <linux/types.h>
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/* Number of elements in the array with statical CDBs */
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#define MAX_STAT_DMA_CDBS 16
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/* Number of DMA engines available on the contoller */
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#define DMA_ENGINES_NUM 2
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/* Maximum h/w supported number of destinations */
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#define DMA_DEST_MAX_NUM 2
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/* FIFO's params */
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#define DMA0_FIFO_SIZE 0x1000
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#define DMA1_FIFO_SIZE 0x1000
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#define DMA_FIFO_ENABLE (1<<12)
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/* DMA Configuration Register. Data Transfer Engine PLB Priority: */
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#define DMA_CFG_DXEPR_LP (0<<26)
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#define DMA_CFG_DXEPR_HP (3<<26)
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#define DMA_CFG_DXEPR_HHP (2<<26)
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#define DMA_CFG_DXEPR_HHHP (1<<26)
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/* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
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#define DMA_CFG_DFMPP_LP (0<<23)
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#define DMA_CFG_DFMPP_HP (3<<23)
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#define DMA_CFG_DFMPP_HHP (2<<23)
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#define DMA_CFG_DFMPP_HHHP (1<<23)
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/* DMA Configuration Register. Force 64-byte Alignment */
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#define DMA_CFG_FALGN (1 << 19)
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/*UIC0:*/
|
||||
#define D0CPF_INT (1<<12)
|
||||
#define D0CSF_INT (1<<11)
|
||||
#define D1CPF_INT (1<<10)
|
||||
#define D1CSF_INT (1<<9)
|
||||
/*UIC1:*/
|
||||
#define DMAE_INT (1<<9)
|
||||
|
||||
/* I2O IOP Interrupt Mask Register */
|
||||
#define I2O_IOPIM_P0SNE (1<<3)
|
||||
#define I2O_IOPIM_P0EM (1<<5)
|
||||
#define I2O_IOPIM_P1SNE (1<<6)
|
||||
#define I2O_IOPIM_P1EM (1<<8)
|
||||
|
||||
/* DMA CDB fields */
|
||||
#define DMA_CDB_MSK (0xF)
|
||||
#define DMA_CDB_64B_ADDR (1<<2)
|
||||
#define DMA_CDB_NO_INT (1<<3)
|
||||
#define DMA_CDB_STATUS_MSK (0x3)
|
||||
#define DMA_CDB_ADDR_MSK (0xFFFFFFF0)
|
||||
|
||||
/* DMA CDB OpCodes */
|
||||
#define DMA_CDB_OPC_NO_OP (0x00)
|
||||
#define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
|
||||
#define DMA_CDB_OPC_MULTICAST (0x05)
|
||||
#define DMA_CDB_OPC_DFILL128 (0x24)
|
||||
#define DMA_CDB_OPC_DCHECK128 (0x23)
|
||||
|
||||
#define DMA_CUED_XOR_BASE (0x10000000)
|
||||
#define DMA_CUED_XOR_HB (0x00000008)
|
||||
|
||||
#ifdef CONFIG_440SP
|
||||
#define DMA_CUED_MULT1_OFF 0
|
||||
#define DMA_CUED_MULT2_OFF 8
|
||||
#define DMA_CUED_MULT3_OFF 16
|
||||
#define DMA_CUED_REGION_OFF 24
|
||||
#define DMA_CUED_XOR_WIN_MSK (0xFC000000)
|
||||
#else
|
||||
#define DMA_CUED_MULT1_OFF 2
|
||||
#define DMA_CUED_MULT2_OFF 10
|
||||
#define DMA_CUED_MULT3_OFF 18
|
||||
#define DMA_CUED_REGION_OFF 26
|
||||
#define DMA_CUED_XOR_WIN_MSK (0xF0000000)
|
||||
#endif
|
||||
|
||||
#define DMA_CUED_REGION_MSK 0x3
|
||||
#define DMA_RXOR123 0x0
|
||||
#define DMA_RXOR124 0x1
|
||||
#define DMA_RXOR125 0x2
|
||||
#define DMA_RXOR12 0x3
|
||||
|
||||
/* S/G addresses */
|
||||
#define DMA_CDB_SG_SRC 1
|
||||
#define DMA_CDB_SG_DST1 2
|
||||
#define DMA_CDB_SG_DST2 3
|
||||
|
||||
/*
|
||||
* DMAx engines Command Descriptor Block Type
|
||||
*/
|
||||
struct dma_cdb {
|
||||
/*
|
||||
* Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
|
||||
*/
|
||||
u8 pad0[2]; /* reserved */
|
||||
u8 attr; /* attributes */
|
||||
u8 opc; /* opcode */
|
||||
u32 sg1u; /* upper SG1 address */
|
||||
u32 sg1l; /* lower SG1 address */
|
||||
u32 cnt; /* SG count, 3B used */
|
||||
u32 sg2u; /* upper SG2 address */
|
||||
u32 sg2l; /* lower SG2 address */
|
||||
u32 sg3u; /* upper SG3 address */
|
||||
u32 sg3l; /* lower SG3 address */
|
||||
};
|
||||
|
||||
/*
|
||||
* DMAx hardware registers (p.515 in 440SPe UM 1.22)
|
||||
*/
|
||||
struct dma_regs {
|
||||
u32 cpfpl;
|
||||
u32 cpfph;
|
||||
u32 csfpl;
|
||||
u32 csfph;
|
||||
u32 dsts;
|
||||
u32 cfg;
|
||||
u8 pad0[0x8];
|
||||
u16 cpfhp;
|
||||
u16 cpftp;
|
||||
u16 csfhp;
|
||||
u16 csftp;
|
||||
u8 pad1[0x8];
|
||||
u32 acpl;
|
||||
u32 acph;
|
||||
u32 s1bpl;
|
||||
u32 s1bph;
|
||||
u32 s2bpl;
|
||||
u32 s2bph;
|
||||
u32 s3bpl;
|
||||
u32 s3bph;
|
||||
u8 pad2[0x10];
|
||||
u32 earl;
|
||||
u32 earh;
|
||||
u8 pad3[0x8];
|
||||
u32 seat;
|
||||
u32 sead;
|
||||
u32 op;
|
||||
u32 fsiz;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2O hardware registers (p.528 in 440SPe UM 1.22)
|
||||
*/
|
||||
struct i2o_regs {
|
||||
u32 ists;
|
||||
u32 iseat;
|
||||
u32 isead;
|
||||
u8 pad0[0x14];
|
||||
u32 idbel;
|
||||
u8 pad1[0xc];
|
||||
u32 ihis;
|
||||
u32 ihim;
|
||||
u8 pad2[0x8];
|
||||
u32 ihiq;
|
||||
u32 ihoq;
|
||||
u8 pad3[0x8];
|
||||
u32 iopis;
|
||||
u32 iopim;
|
||||
u32 iopiq;
|
||||
u8 iopoq;
|
||||
u8 pad4[3];
|
||||
u16 iiflh;
|
||||
u16 iiflt;
|
||||
u16 iiplh;
|
||||
u16 iiplt;
|
||||
u16 ioflh;
|
||||
u16 ioflt;
|
||||
u16 ioplh;
|
||||
u16 ioplt;
|
||||
u32 iidc;
|
||||
u32 ictl;
|
||||
u32 ifcpp;
|
||||
u8 pad5[0x4];
|
||||
u16 mfac0;
|
||||
u16 mfac1;
|
||||
u16 mfac2;
|
||||
u16 mfac3;
|
||||
u16 mfac4;
|
||||
u16 mfac5;
|
||||
u16 mfac6;
|
||||
u16 mfac7;
|
||||
u16 ifcfh;
|
||||
u16 ifcht;
|
||||
u8 pad6[0x4];
|
||||
u32 iifmc;
|
||||
u32 iodb;
|
||||
u32 iodbc;
|
||||
u32 ifbal;
|
||||
u32 ifbah;
|
||||
u32 ifsiz;
|
||||
u32 ispd0;
|
||||
u32 ispd1;
|
||||
u32 ispd2;
|
||||
u32 ispd3;
|
||||
u32 ihipl;
|
||||
u32 ihiph;
|
||||
u32 ihopl;
|
||||
u32 ihoph;
|
||||
u32 iiipl;
|
||||
u32 iiiph;
|
||||
u32 iiopl;
|
||||
u32 iioph;
|
||||
u32 ifcpl;
|
||||
u32 ifcph;
|
||||
u8 pad7[0x8];
|
||||
u32 iopt;
|
||||
};
|
||||
|
||||
#endif /* _PPC440SPE_DMA_H */
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* 440SPe's XOR engines support header file
|
||||
*
|
||||
* 2006-2009 (C) DENX Software Engineering.
|
||||
*
|
||||
* Author: Yuri Tikhonov <yur@emcraft.com>
|
||||
*
|
||||
* This file is licensed under the term of the GNU General Public License
|
||||
* version 2. The program licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef _PPC440SPE_XOR_H
|
||||
#define _PPC440SPE_XOR_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Number of XOR engines available on the contoller */
|
||||
#define XOR_ENGINES_NUM 1
|
||||
|
||||
/* Number of operands supported in the h/w */
|
||||
#define XOR_MAX_OPS 16
|
||||
|
||||
/*
|
||||
* XOR Command Block Control Register bits
|
||||
*/
|
||||
#define XOR_CBCR_LNK_BIT (1<<31) /* link present */
|
||||
#define XOR_CBCR_TGT_BIT (1<<30) /* target present */
|
||||
#define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
|
||||
#define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
|
||||
#define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
|
||||
#define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
|
||||
|
||||
/*
|
||||
* XORCore Status Register bits
|
||||
*/
|
||||
#define XOR_SR_XCP_BIT (1<<31) /* core processing */
|
||||
#define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
|
||||
#define XOR_SR_IC_BIT (1<<16) /* invalid command */
|
||||
#define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
|
||||
#define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
|
||||
#define XOR_SR_CBC_BIT (1<<1) /* CB complete */
|
||||
#define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
|
||||
|
||||
/*
|
||||
* XORCore Control Set and Reset Register bits
|
||||
*/
|
||||
#define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
|
||||
#define XOR_CRSR_XAE_BIT (1<<30) /* enable */
|
||||
#define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
|
||||
#define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
|
||||
#define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
|
||||
#define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
|
||||
|
||||
/*
|
||||
* XORCore Interrupt Enable Register
|
||||
*/
|
||||
#define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
|
||||
#define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
|
||||
#define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
|
||||
#define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
|
||||
#define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
|
||||
|
||||
/*
|
||||
* XOR Accelerator engine Command Block Type
|
||||
*/
|
||||
struct xor_cb {
|
||||
/*
|
||||
* Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
|
||||
*/
|
||||
u32 cbc; /* control */
|
||||
u32 cbbc; /* byte count */
|
||||
u32 cbs; /* status */
|
||||
u8 pad0[4]; /* reserved */
|
||||
u32 cbtah; /* target address high */
|
||||
u32 cbtal; /* target address low */
|
||||
u32 cblah; /* link address high */
|
||||
u32 cblal; /* link address low */
|
||||
struct {
|
||||
u32 h;
|
||||
u32 l;
|
||||
} __attribute__ ((packed)) ops[16];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/*
|
||||
* XOR hardware registers Table 19-3, UM 1.22
|
||||
*/
|
||||
struct xor_regs {
|
||||
u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
|
||||
u8 pad0[352]; /* reserved */
|
||||
u32 cbcr; /* CB control register */
|
||||
u32 cbbcr; /* CB byte count register */
|
||||
u32 cbsr; /* CB status register */
|
||||
u8 pad1[4]; /* reserved */
|
||||
u32 cbtahr; /* operand target address high register */
|
||||
u32 cbtalr; /* operand target address low register */
|
||||
u32 cblahr; /* CB link address high register */
|
||||
u32 cblalr; /* CB link address low register */
|
||||
u32 crsr; /* control set register */
|
||||
u32 crrr; /* control reset register */
|
||||
u32 ccbahr; /* current CB address high register */
|
||||
u32 ccbalr; /* current CB address low register */
|
||||
u32 plbr; /* PLB configuration register */
|
||||
u32 ier; /* interrupt enable register */
|
||||
u32 pecr; /* parity error count register */
|
||||
u32 sr; /* status register */
|
||||
u32 revidr; /* revision ID register */
|
||||
};
|
||||
|
||||
#endif /* _PPC440SPE_XOR_H */
|
||||
Loading…
Reference in New Issue