MLK-24171-5 PCI: imx8mp: verify the pcie internal pll reference clock
- Verify the both internal PLL_SYS and external OSC reference clock modes on iMX8MP EVK board, and pass the PCIe compliance tests. - Remove the no-needed bypass setting. - PHY configration should be completed before CMN_RSTN is set to 1b1 - To manually initiate the speed change to make sure GEN2 is linked up: - Write to LINK_CONTROL2_LINK_STATUS2_REG.PCIE_CAP_TARGET_LINK_SPEED in the local device - De-assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device - Assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>5.4-rM2-2.2.x-imx-squashed
Richard Zhu
parent
0a91df355e
commit
12589ba98b
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@ -40,7 +40,7 @@
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#include "pcie-designware.h"
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#define IMX8MQ_PCIE_LINK_CAP_REG_OFFSET 0x7c
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#define IMX8MQ_PCIE_LINK_CAP_L1EL_64US (BIT(18) | BIT(17))
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#define IMX8MQ_PCIE_LINK_CAP_L1EL_64US GENMASK(18, 17)
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#define IMX8MQ_PCIE_L1SUB_CTRL1_REG_EN_MASK 0xf
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#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
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#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
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@ -62,15 +62,16 @@
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#define IMX8MP_GPR_REG2_P_PLL (0xc << 0)
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#define IMX8MP_GPR_REG2_M_PLL (0x320 << 6)
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#define IMX8MP_GPR_REG2_S_PLL (0x4 << 16)
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#define IMX8MP_GPR_REG2_BYPASS_PLL BIT(21)
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#define IMX8MP_GPR_REG3 0xc
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#define IMX8MP_GPR_REG3_PLL_CKE BIT(17)
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#define IMX8MP_GPR_REG3_PLL_EXT_BYPASS BIT(18)
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#define IMX8MP_GPR_REG3_PLL_RST BIT(31)
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#define IMX8MP_GPR_PCIE_SSC_EN BIT(16)
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#define IMX8MP_GPR_PCIE_PWR_OFF BIT(17)
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#define IMX8MP_GPR_PCIE_CMN_RSTN BIT(18)
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#define IMX8MP_GPR_PCIE_AUX_EN BIT(19)
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#define IMX8MP_GPR_PCIE_REF_SEL_MASK GENMASK(25, 24)
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#define IMX8MP_GPR_PCIE_REF_PLL (BIT(24) | BIT(25))
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#define IMX8MP_GPR_PCIE_REF_PLL_SYS GENMASK(25, 24)
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#define IMX8MP_GPR_PCIE_REF_EXT_OSC BIT(25)
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#define IMX8MP_GPR_PCIE_REF_EXT_XO BIT(24)
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#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
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@ -176,6 +177,7 @@ struct imx6_pcie {
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
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#define PCIE_RC_LCSR 0x80
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#define PCIE_RC_LC2SR 0xa0
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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@ -1027,7 +1029,9 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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/* fall through */
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case IMX8MP:
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case IMX8MP_EP:
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reset_control_assert(imx6_pcie->apps_reset);
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imx6_pcie_ltssm_disable(dev);
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reset_control_assert(imx6_pcie->pciephy_reset);
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reset_control_assert(imx6_pcie->pciephy_perst);
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break;
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case IMX6SX:
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case IMX6SX_EP:
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@ -1250,14 +1254,30 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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break;
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case IMX8MP:
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case IMX8MP_EP:
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if (phy_power_on(imx6_pcie->phy) < 0)
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dev_err(dev, "Failed to power on PHY!\n");
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reset_control_assert(imx6_pcie->pciephy_perst);
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reset_control_assert(imx6_pcie->pciephy_reset);
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udelay(10);
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reset_control_deassert(imx6_pcie->pciephy_reset);
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reset_control_deassert(imx6_pcie->pciephy_perst);
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/* release pcie_phy_apb_reset and pcie_phy_init_resetn */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG0);
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val |= IMX8MP_GPR_REG0_PHY_APB_RST;
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val |= IMX8MP_GPR_REG0_PHY_INIT_RST;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG0);
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val = imx6_pcie_grp_offset(imx6_pcie);
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if (imx6_pcie->ext_osc) {
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/*TODO Configure the external OSC as REF clock */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_REF_SEL_MASK,
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IMX8MP_GPR_PCIE_REF_SEL_MASK);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_AUX_EN,
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IMX8MP_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_PWR_OFF, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_CMN_RSTN, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_REF_SEL_MASK,
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IMX8MP_GPR_PCIE_REF_EXT_OSC);
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@ -1265,20 +1285,19 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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/* Configure the internal PLL as REF clock */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_REF_SEL_MASK,
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IMX8MP_GPR_PCIE_REF_PLL);
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IMX8MP_GPR_PCIE_REF_PLL_SYS);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_AUX_EN,
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IMX8MP_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_PWR_OFF, 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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IMX8MP_GPR_PCIE_CMN_RSTN, 0);
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}
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udelay(100);
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/* release pcie_phy_apb_reset and pcie_phy_init_resetn */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG0);
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val |= IMX8MP_GPR_REG0_PHY_APB_RST;
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val |= IMX8MP_GPR_REG0_PHY_INIT_RST;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG0);
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udelay(1);
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/* turn off pcie ltssm */
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imx6_pcie_ltssm_disable(dev);
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phy_calibrate(imx6_pcie->phy);
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/*
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* GPR_PCIE_PHY_CTRL_BUS[3:0]
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* 0:i_ssc_en 1:i_power_off
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@ -1286,12 +1305,8 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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*/
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val = imx6_pcie_grp_offset(imx6_pcie);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
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BIT(18),
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BIT(18));
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udelay(200);
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reset_control_deassert(imx6_pcie->pciephy_reset);
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udelay(10);
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IMX8MP_GPR_PCIE_CMN_RSTN,
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IMX8MP_GPR_PCIE_CMN_RSTN);
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imx8_pcie_wait_for_phy_pll_lock(imx6_pcie);
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@ -1582,14 +1597,12 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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break;
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case IMX8MP:
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case IMX8MP_EP:
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phy_power_on(imx6_pcie->phy);
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dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n",
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imx6_pcie->ext_osc ? "EXT" : "PLL");
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imx6_pcie_clk_enable(imx6_pcie);
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/*
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* Make sure that the bypass_pll of gpr_reg2 is set to
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* 1'b1. Set P=12,M=800,S=4 and must set ICP=2'b01.
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*/
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/* Set P=12,M=800,S=4 and must set ICP=2'b01. */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG2);
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val &= ~IMX8MP_GPR_REG2_P_PLL_MASK;
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val |= IMX8MP_GPR_REG2_P_PLL;
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@ -1597,29 +1610,17 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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val |= IMX8MP_GPR_REG2_M_PLL;
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val &= ~IMX8MP_GPR_REG2_S_PLL_MASK;
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val |= IMX8MP_GPR_REG2_S_PLL;
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val |= IMX8MP_GPR_REG2_BYPASS_PLL;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG2);
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/* wait greater than 1/F_FREF =1/2MHZ=0.5us */
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udelay(1);
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/* release reset */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG3);
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val |= IMX8MP_GPR_REG3_PLL_RST;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG3);
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udelay(10);
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/*
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* Make sure that the pll_ext_bypass of gpr_reg3 is set
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* to 1'b0. set 1 to pll_cke of GPR_REG3
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*/
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG2);
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val &= ~IMX8MP_GPR_REG2_BYPASS_PLL;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG2);
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/*
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* Make sure that the pll_ext_bypass of gpr_reg3 is set
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* to 1'b0. set 1 to pll_cke of GPR_REG3
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*/
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/* Set 1 to pll_cke of GPR_REG3 */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG3);
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val &= ~IMX8MP_GPR_REG3_PLL_EXT_BYPASS;
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val |= IMX8MP_GPR_REG3_PLL_CKE;
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writel(val, imx6_pcie->hsmix_base + IMX8MP_GPR_REG3);
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@ -1631,10 +1632,12 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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break;
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udelay(10);
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}
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if (i >= 100) {
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if (i >= 100)
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dev_err(imx6_pcie->pci->dev,
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"PCIe PHY PLL clock is not locked.\n");
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}
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else
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dev_info(imx6_pcie->pci->dev,
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"PCIe PHY PLL clock is locked.\n");
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/* pcie_clock_module_en */
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val = readl(imx6_pcie->hsmix_base + IMX8MP_GPR_REG0);
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@ -1809,12 +1812,21 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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/* Start LTSSM. */
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imx6_pcie_ltssm_enable(dev);
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ret = dw_pcie_wait_for_link(pci);
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if (ret)
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goto err_reset_phy;
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if (imx6_pcie->link_gen >= 2) {
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/* Fill up target link speed before speed change. */
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tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LC2SR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= imx6_pcie->link_gen;
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dw_pcie_writel_dbi(pci, PCIE_RC_LC2SR, tmp);
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tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp &= ~PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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/* Allow Gen2 mode after the link is up. */
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tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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