iwlwifi: refactor tx byte count table usage
This patch drops unreadable usage of IWL_SET/GET_BITS16 in byte count tables handling This patch also cleans a bit the byte count table code and adds WARN_ON traps on invalid values This patch is pure cleanup, no functional changes. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Cc: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -111,7 +111,6 @@
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#define PCI_CFG_CMD_REG_INT_DIS_MSK 0x04
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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#define TFD_QUEUE_SIZE_MAX (256)
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#define IWL_NUM_SCAN_RATES (2)
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@ -815,8 +814,6 @@ enum {
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* up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
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* in DRAM containing 256 Transmit Frame Descriptors (TFDs).
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*/
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#define IWL49_MAX_WIN_SIZE 64
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#define IWL49_QUEUE_SIZE 256
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#define IWL49_NUM_FIFOS 7
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#define IWL49_CMD_FIFO_NUM 4
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#define IWL49_NUM_QUEUES 16
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@ -882,26 +879,7 @@ struct iwl_tfd {
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/**
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* struct iwl4965_queue_byte_cnt_entry
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*
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* Byte Count Table Entry
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*
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* Bit fields:
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* 15-12: reserved
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* 11- 0: total to-be-transmitted byte count of frame (does not include command)
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*/
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struct iwl4965_queue_byte_cnt_entry {
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__le16 val;
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/* __le16 byte_cnt:12; */
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#define IWL_byte_cnt_POS 0
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#define IWL_byte_cnt_LEN 12
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#define IWL_byte_cnt_SYM val
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/* __le16 rsvd:4; */
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} __attribute__ ((packed));
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/**
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* struct iwl4965_sched_queue_byte_cnt_tbl
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* struct iwl4965_schedq_bc_tbl
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*
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* Byte Count table
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*
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@ -915,15 +893,12 @@ struct iwl4965_queue_byte_cnt_entry {
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* count table for the chosen Tx queue. If the TFD index is 0-63, the driver
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* must duplicate the byte count entry in corresponding index 256-319.
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*
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* "dont_care" padding puts each byte count table on a 1024-byte boundary;
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* padding puts each byte count table on a 1024-byte boundary;
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* 4965 assumes tables are separated by 1024 bytes.
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*/
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struct iwl4965_sched_queue_byte_cnt_tbl {
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struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL49_QUEUE_SIZE +
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IWL49_MAX_WIN_SIZE];
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u8 dont_care[1024 -
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(IWL49_QUEUE_SIZE + IWL49_MAX_WIN_SIZE) *
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sizeof(__le16)];
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struct iwl4965_schedq_bc_tbl {
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__le16 tfd_offset[TFD_QUEUE_BC_SIZE];
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u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
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} __attribute__ ((packed));
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@ -951,8 +926,7 @@ struct iwl4965_sched_queue_byte_cnt_tbl {
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* 31- 0: Not used
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*/
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struct iwl4965_shared {
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struct iwl4965_sched_queue_byte_cnt_tbl
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queues_byte_cnt_tbls[IWL49_NUM_QUEUES];
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struct iwl4965_schedq_bc_tbl queues_bc_tbls[IWL49_NUM_QUEUES];
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__le32 rb_closed;
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/* __le32 rb_closed_stts_rb_num:12; */
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@ -716,7 +716,7 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
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/* Tel 4965 where to find Tx byte count tables */
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iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
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(priv->shared_phys +
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offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
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offsetof(struct iwl4965_shared, queues_bc_tbls)) >> 10);
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/* Disable chain mode for all queues */
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iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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@ -1668,21 +1668,22 @@ static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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struct iwl_tx_queue *txq,
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u16 byte_cnt)
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{
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int len;
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int txq_id = txq->q.id;
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struct iwl4965_shared *shared_data = priv->shared_virt;
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int txq_id = txq->q.id;
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int write_ptr = txq->q.write_ptr;
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int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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__le16 bc_ent;
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len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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bc_ent = cpu_to_le16(len & 0xFFF);
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/* Set up byte count within first 256 entries */
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[txq->q.write_ptr], byte_cnt, len);
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shared_data->queues_bc_tbls[txq_id].tfd_offset[write_ptr] = bc_ent;
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/* If within first 64 entries, duplicate at end */
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if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
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byte_cnt, len);
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if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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shared_data->queues_bc_tbls[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
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}
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/**
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@ -76,30 +76,31 @@
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/* EERPROM */
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#define IWL_5000_EEPROM_IMG_SIZE 2048
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#define IWL50_MAX_WIN_SIZE 64
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#define IWL50_QUEUE_SIZE 256
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#define IWL50_CMD_FIFO_NUM 7
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#define IWL50_NUM_QUEUES 20
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#define IWL50_NUM_AMPDU_QUEUES 10
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#define IWL50_FIRST_AMPDU_QUEUE 10
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#define IWL_sta_id_POS 12
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#define IWL_sta_id_LEN 4
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#define IWL_sta_id_SYM val
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/* Fixed (non-configurable) rx data from phy */
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/* Base physical address of iwl5000_shared is provided to SCD_DRAM_BASE_ADDR
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* and &iwl5000_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
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struct iwl5000_sched_queue_byte_cnt_tbl {
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struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL50_QUEUE_SIZE +
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IWL50_MAX_WIN_SIZE];
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/**
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* struct iwl5000_schedq_bc_tbl scheduler byte count table
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* base physical address of iwl5000_shared
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* is provided to SCD_DRAM_BASE_ADDR
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* @tfd_offset 0-12 - tx command byte count
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* 12-16 - station index
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*/
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struct iwl5000_schedq_bc_tbl {
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__le16 tfd_offset[TFD_QUEUE_BC_SIZE];
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} __attribute__ ((packed));
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/**
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* struct iwl5000_shared
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* @rb_closed
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* address is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG
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*/
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struct iwl5000_shared {
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struct iwl5000_sched_queue_byte_cnt_tbl
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queues_byte_cnt_tbls[IWL50_NUM_QUEUES];
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struct iwl5000_schedq_bc_tbl queues_bc_tbls[IWL50_NUM_QUEUES];
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__le32 rb_closed;
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/* __le32 rb_closed_stts_rb_num:12; */
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@ -723,7 +723,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
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iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
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(priv->shared_phys +
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offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
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offsetof(struct iwl5000_shared, queues_bc_tbls)) >> 10);
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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IWL50_SCD_QUEUECHAIN_SEL_ALL(
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priv->hw_params.max_txq_num));
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@ -891,15 +891,17 @@ static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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u16 byte_cnt)
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{
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struct iwl5000_shared *shared_data = priv->shared_virt;
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int write_ptr = txq->q.write_ptr;
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int txq_id = txq->q.id;
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u8 sec_ctl = 0;
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u8 sta = 0;
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int len;
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u8 sta_id = 0;
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u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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__le16 bc_ent;
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len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM) {
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sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
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switch (sec_ctl & TX_CMD_SEC_MSK) {
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@ -915,40 +917,36 @@ static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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}
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}
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[txq->q.write_ptr], byte_cnt, len);
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bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[txq->q.write_ptr], sta_id, sta);
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shared_data->queues_bc_tbls[txq_id].tfd_offset[write_ptr] = bc_ent;
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if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
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byte_cnt, len);
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
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sta_id, sta);
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}
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if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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shared_data->queues_bc_tbls[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
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}
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static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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struct iwl_tx_queue *txq)
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{
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int txq_id = txq->q.id;
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struct iwl5000_shared *shared_data = priv->shared_virt;
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u8 sta = 0;
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int txq_id = txq->q.id;
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int read_ptr = txq->q.read_ptr;
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u8 sta_id = 0;
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__le16 bc_ent;
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != IWL_CMD_QUEUE_NUM)
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sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
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sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
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val = cpu_to_le16(1 | (sta << 12));
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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shared_data->queues_bc_tbls[txq_id].
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tfd_offset[read_ptr] = bc_ent;
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if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
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shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
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val = cpu_to_le16(1 | (sta << 12));
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}
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if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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shared_data->queues_bc_tbls[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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}
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static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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@ -393,4 +393,9 @@
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/* TCSR: tx_config register values */
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#define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF) /* bits 0-13 */
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#define TFD_QUEUE_SIZE_MAX (256)
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#define TFD_QUEUE_SIZE_BC_DUP (64)
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#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
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#endif /* !__iwl_fh_h__ */
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@ -32,108 +32,6 @@
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#include <linux/ctype.h>
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/*
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* The structures defined by the hardware/uCode interface
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* have bit-wise operations. For each bit-field there is
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* a data symbol in the structure, the start bit position
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* and the length of the bit-field.
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*
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* iwl_get_bits and iwl_set_bits will return or set the
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* appropriate bits on a 32-bit value.
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*
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* IWL_GET_BITS and IWL_SET_BITS use symbol expansion to
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* expand out to the appropriate call to iwl_get_bits
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* and iwl_set_bits without having to reference all of the
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* numerical constants and defines provided in the hardware
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* definition
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*/
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/**
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* iwl_get_bits - Extract a hardware bit-field value
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* @src: source hardware value (__le32)
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* @pos: bit-position (0-based) of first bit of value
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* @len: length of bit-field
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*
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* iwl_get_bits will return the bit-field in cpu endian ordering.
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*
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* NOTE: If used from IWL_GET_BITS then pos and len are compile-constants and
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* will collapse to minimal code by the compiler.
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*/
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static inline u32 iwl_get_bits(__le32 src, u8 pos, u8 len)
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{
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u32 tmp = le32_to_cpu(src);
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tmp >>= pos;
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tmp &= (1UL << len) - 1;
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return tmp;
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}
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/**
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* iwl_set_bits - Set a hardware bit-field value
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* @dst: Address of __le32 hardware value
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* @pos: bit-position (0-based) of first bit of value
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* @len: length of bit-field
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* @val: cpu endian value to encode into the bit-field
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*
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* iwl_set_bits will encode val into dst, masked to be len bits long at bit
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* position pos.
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*
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* NOTE: If used IWL_SET_BITS pos and len will be compile-constants and
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* will collapse to minimal code by the compiler.
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*/
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static inline void iwl_set_bits(__le32 *dst, u8 pos, u8 len, int val)
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{
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u32 tmp = le32_to_cpu(*dst);
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tmp &= ~(((1UL << len) - 1) << pos);
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tmp |= (val & ((1UL << len) - 1)) << pos;
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*dst = cpu_to_le32(tmp);
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}
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static inline void iwl_set_bits16(__le16 *dst, u8 pos, u8 len, int val)
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{
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u16 tmp = le16_to_cpu(*dst);
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tmp &= ~((1UL << (pos + len)) - (1UL << pos));
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tmp |= (val & ((1UL << len) - 1)) << pos;
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*dst = cpu_to_le16(tmp);
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}
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/*
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* The bit-field definitions in iwl-xxxx-hw.h are in the form of:
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*
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* struct example {
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* __le32 val1;
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* #define IWL_name_POS 8
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* #define IWL_name_LEN 4
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* #define IWL_name_SYM val1
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* };
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*
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* The IWL_SET_BITS and IWL_GET_BITS macros are provided to allow the driver
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* to call:
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*
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* struct example bar;
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* u32 val = IWL_GET_BITS(bar, name);
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* val = val * 2;
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* IWL_SET_BITS(bar, name, val);
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*
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* All cpu / host ordering, masking, and shifts are performed by the macros
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* and iwl_{get,set}_bits.
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*
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*/
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#define IWL_SET_BITS(s, sym, v) \
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iwl_set_bits(&(s).IWL_ ## sym ## _SYM, IWL_ ## sym ## _POS, \
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IWL_ ## sym ## _LEN, (v))
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#define IWL_SET_BITS16(s, sym, v) \
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iwl_set_bits16(&(s).IWL_ ## sym ## _SYM, IWL_ ## sym ## _POS, \
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IWL_ ## sym ## _LEN, (v))
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#define IWL_GET_BITS(s, sym) \
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iwl_get_bits((s).IWL_ ## sym ## _SYM, IWL_ ## sym ## _POS, \
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IWL_ ## sym ## _LEN)
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#define KELVIN_TO_CELSIUS(x) ((x)-273)
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#define CELSIUS_TO_KELVIN(x) ((x)+273)
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#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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