net/mlx5e: Add port buffer's congestion counters
Add 3 counters per priority to ethtool using PPCNT: 1) rx_prio[p]_buf_discard - the number of packets discarded by device due to lack of per host receive buffers 2) rx_prio[p]_cong_discard - the number of packets discarded by device due to per host congestion 3) rx_prio[p]_marked - the number of packets ECN marked by device due to per host congestion Signed-off-by: Aya Levin <ayal@mellanox.com> Reviewed-by: Moshe Shemesh <moshe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>alistair/sunxi64-5.4-dsi
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948d3f90e9
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1297d97f48
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@ -981,6 +981,147 @@ static void mlx5e_grp_pcie_update_stats(struct mlx5e_priv *priv)
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
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}
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}
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#define PPORT_PER_TC_PRIO_OFF(c) \
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MLX5_BYTE_OFF(ppcnt_reg, \
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counter_set.eth_per_tc_prio_grp_data_layout.c##_high)
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static const struct counter_desc pport_per_tc_prio_stats_desc[] = {
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{ "rx_prio%d_buf_discard", PPORT_PER_TC_PRIO_OFF(no_buffer_discard_uc) },
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};
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#define NUM_PPORT_PER_TC_PRIO_COUNTERS ARRAY_SIZE(pport_per_tc_prio_stats_desc)
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#define PPORT_PER_TC_CONGEST_PRIO_OFF(c) \
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MLX5_BYTE_OFF(ppcnt_reg, \
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counter_set.eth_per_tc_congest_prio_grp_data_layout.c##_high)
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static const struct counter_desc pport_per_tc_congest_prio_stats_desc[] = {
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{ "rx_prio%d_cong_discard", PPORT_PER_TC_CONGEST_PRIO_OFF(wred_discard) },
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{ "rx_prio%d_marked", PPORT_PER_TC_CONGEST_PRIO_OFF(ecn_marked_tc) },
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};
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#define NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS \
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ARRAY_SIZE(pport_per_tc_congest_prio_stats_desc)
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static int mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv *priv)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return 0;
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return NUM_PPORT_PER_TC_PRIO_COUNTERS * NUM_PPORT_PRIO;
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}
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static int mlx5e_grp_per_port_buffer_congest_fill_strings(struct mlx5e_priv *priv,
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u8 *data, int idx)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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int i, prio;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return idx;
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
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sprintf(data + (idx++) * ETH_GSTRING_LEN,
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pport_per_tc_prio_stats_desc[i].format, prio);
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for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++)
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sprintf(data + (idx++) * ETH_GSTRING_LEN,
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pport_per_tc_congest_prio_stats_desc[i].format, prio);
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}
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return idx;
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}
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static int mlx5e_grp_per_port_buffer_congest_fill_stats(struct mlx5e_priv *priv,
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u64 *data, int idx)
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{
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struct mlx5e_pport_stats *pport = &priv->stats.pport;
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struct mlx5_core_dev *mdev = priv->mdev;
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int i, prio;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return idx;
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
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data[idx++] =
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MLX5E_READ_CTR64_BE(&pport->per_tc_prio_counters[prio],
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pport_per_tc_prio_stats_desc, i);
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for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++)
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data[idx++] =
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MLX5E_READ_CTR64_BE(&pport->per_tc_congest_prio_counters[prio],
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pport_per_tc_congest_prio_stats_desc, i);
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}
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return idx;
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}
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static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv)
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{
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struct mlx5e_pport_stats *pstats = &priv->stats.pport;
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struct mlx5_core_dev *mdev = priv->mdev;
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u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
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int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
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void *out;
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int prio;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return;
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MLX5_SET(ppcnt_reg, in, pnat, 2);
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MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP);
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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out = pstats->per_tc_prio_counters[prio];
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MLX5_SET(ppcnt_reg, in, prio_tc, prio);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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}
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}
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static int mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv *priv)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return 0;
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return NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS * NUM_PPORT_PRIO;
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}
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static void mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv *priv)
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{
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struct mlx5e_pport_stats *pstats = &priv->stats.pport;
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struct mlx5_core_dev *mdev = priv->mdev;
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u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
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int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
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void *out;
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int prio;
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if (!MLX5_CAP_GEN(mdev, sbcam_reg))
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return;
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MLX5_SET(ppcnt_reg, in, pnat, 2);
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MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP);
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for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
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out = pstats->per_tc_congest_prio_counters[prio];
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MLX5_SET(ppcnt_reg, in, prio_tc, prio);
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mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
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}
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}
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static int mlx5e_grp_per_port_buffer_congest_get_num_stats(struct mlx5e_priv *priv)
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{
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return mlx5e_grp_per_tc_prio_get_num_stats(priv) +
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mlx5e_grp_per_tc_congest_prio_get_num_stats(priv);
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}
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static void mlx5e_grp_per_port_buffer_congest_update_stats(struct mlx5e_priv *priv)
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{
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mlx5e_grp_per_tc_prio_update_stats(priv);
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mlx5e_grp_per_tc_congest_prio_update_stats(priv);
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}
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#define PPORT_PER_PRIO_OFF(c) \
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#define PPORT_PER_PRIO_OFF(c) \
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MLX5_BYTE_OFF(ppcnt_reg, \
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MLX5_BYTE_OFF(ppcnt_reg, \
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counter_set.eth_per_prio_grp_data_layout.c##_high)
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counter_set.eth_per_prio_grp_data_layout.c##_high)
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@ -1610,7 +1751,13 @@ const struct mlx5e_stats_grp mlx5e_stats_grps[] = {
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.get_num_stats = mlx5e_grp_channels_get_num_stats,
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.get_num_stats = mlx5e_grp_channels_get_num_stats,
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.fill_strings = mlx5e_grp_channels_fill_strings,
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.fill_strings = mlx5e_grp_channels_fill_strings,
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.fill_stats = mlx5e_grp_channels_fill_stats,
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.fill_stats = mlx5e_grp_channels_fill_stats,
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}
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},
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{
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.get_num_stats = mlx5e_grp_per_port_buffer_congest_get_num_stats,
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.fill_strings = mlx5e_grp_per_port_buffer_congest_fill_strings,
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.fill_stats = mlx5e_grp_per_port_buffer_congest_fill_stats,
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.update_stats = mlx5e_grp_per_port_buffer_congest_update_stats,
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},
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};
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};
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const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);
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const int mlx5e_num_stats_grps = ARRAY_SIZE(mlx5e_stats_grps);
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@ -207,6 +207,8 @@ struct mlx5e_pport_stats {
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__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
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__be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
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};
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};
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#define PCIE_PERF_GET(pcie_stats, c) \
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#define PCIE_PERF_GET(pcie_stats, c) \
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