Staging: vt6655: Checkpatch fix: c99 comment headings
This patch fixes some of the following checkpatch.pl errors in mac.h ERROR: do not use C99 // comments This patch reformats all single line c99 style comments to the preferred style. Signed-off-by: Emrys Bayliss <emrys@paradise.net.nz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.1
Emrys Bayliss
Greg Kroah-Hartman
parent
0d12e05799
commit
12b79518fb
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@ -38,11 +38,11 @@
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#include "upc.h"
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/*--------------------- Export Definitions -------------------------*/
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// Registers in the MAC
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/* Registers in the MAC */
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#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
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#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
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// Registers not related to 802.11b
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/* Registers not related to 802.11b */
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#define MAC_REG_BCFG0 0x00
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#define MAC_REG_BCFG1 0x01
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#define MAC_REG_FCR0 0x02
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@ -68,7 +68,7 @@
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#define MAC_REG_TMCTL1 0x19
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#define MAC_REG_TMDATA0 0x1C
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// MAC Parameter related
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/* MAC Parameter related */
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#define MAC_REG_LRT 0x20
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#define MAC_REG_SRT 0x21
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#define MAC_REG_SIFS 0x22
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@ -85,13 +85,13 @@
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#define MAC_REG_ACKFAILCNT 0x2E
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#define MAC_REG_FCSERRCNT 0x2F
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// TSF Related
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/* TSF Related */
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#define MAC_REG_TSFCNTR 0x30
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#define MAC_REG_NEXTTBTT 0x38
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#define MAC_REG_TSFOFST 0x40
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#define MAC_REG_TFTCTL 0x48
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// WMAC Control/Status Related
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/* WMAC Control/Status Related */
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#define MAC_REG_ENCFG 0x4C
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#define MAC_REG_PAGE1SEL 0x4F
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#define MAC_REG_CFG 0x50
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@ -103,7 +103,7 @@
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#define MAC_REG_IMR 0x58
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#define MAC_REG_ISR 0x5C
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// Power Saving Related
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/* Power Saving Related */
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#define MAC_REG_PSCFG 0x60
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#define MAC_REG_PSCTL 0x61
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#define MAC_REG_PSPWRSIG 0x62
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@ -115,7 +115,7 @@
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#define MAC_REG_SYNSPACCNT 0x6A
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#define MAC_REG_WAKSYNOPT 0x6B
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// Baseband/IF Control Group
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/* Baseband/IF Control Group */
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#define MAC_REG_BBREGCTL 0x6C
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#define MAC_REG_CHANNEL 0x6D
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#define MAC_REG_BBREGADR 0x6E
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@ -128,7 +128,7 @@
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#define MAC_REG_GPIOCTL0 0x7A
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#define MAC_REG_GPIOCTL1 0x7B
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// MAC DMA Related Group
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/* MAC DMA Related Group */
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#define MAC_REG_TXDMACTL0 0x7C
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#define MAC_REG_TXDMAPTR0 0x80
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#define MAC_REG_AC0DMACTL 0x84
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@ -144,15 +144,15 @@
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#define MAC_REG_ATIMDMACTL 0xAC
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#define MAC_REG_ATIMDMAPTR 0xB0
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// MiscFF PIO related
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/* MiscFF PIO related */
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#define MAC_REG_MISCFFNDEX 0xB4
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#define MAC_REG_MISCFFCTL 0xB6
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#define MAC_REG_MISCFFDATA 0xB8
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// Extend SW Timer
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/* Extend SW Timer */
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#define MAC_REG_TMDATA1 0xBC
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// WOW Related Group
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/* WOW Related Group */
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#define MAC_REG_WAKEUPEN0 0xC0
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#define MAC_REG_WAKEUPEN1 0xC1
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#define MAC_REG_WAKEUPSR0 0xC2
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@ -162,13 +162,13 @@
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#define MAC_REG_WAKE128_2 0xE4
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#define MAC_REG_WAKE128_3 0xF4
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/////////////// Page 1 ///////////////////
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/************** Page 1 ******************/
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#define MAC_REG_CRC_128_0 0x04
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#define MAC_REG_CRC_128_1 0x06
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#define MAC_REG_CRC_128_2 0x08
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#define MAC_REG_CRC_128_3 0x0A
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// MAC Configuration Group
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/* MAC Configuration Group */
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#define MAC_REG_PAR0 0x0C
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#define MAC_REG_PAR4 0x10
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#define MAC_REG_BSSID0 0x14
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@ -176,7 +176,7 @@
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#define MAC_REG_MAR0 0x1C
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#define MAC_REG_MAR4 0x20
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// MAC RSPPKT INFO Group
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/* MAC RSPPKT INFO Group */
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#define MAC_REG_RSPINF_B_1 0x24
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#define MAC_REG_RSPINF_B_2 0x28
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#define MAC_REG_RSPINF_B_5 0x2C
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@ -191,7 +191,7 @@
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#define MAC_REG_RSPINF_A_54 0x42
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#define MAC_REG_RSPINF_A_72 0x44
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// 802.11h relative
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/* 802.11h relative */
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#define MAC_REG_QUIETINIT 0x60
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#define MAC_REG_QUIETGAP 0x62
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#define MAC_REG_QUIETDUR 0x64
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@ -203,7 +203,7 @@
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#define MAC_REG_PWRCCK 0x73
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#define MAC_REG_PWROFDM 0x7C
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// Bits in the BCFG0 register
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/* Bits in the BCFG0 register */
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#define BCFG0_PERROFF 0x40
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#define BCFG0_MRDMDIS 0x20
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#define BCFG0_MRDLDIS 0x10
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@ -211,7 +211,7 @@
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#define BCFG0_VSERREN 0x02
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#define BCFG0_LATMEN 0x01
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// Bits in the BCFG1 register
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/* Bits in the BCFG1 register */
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#define BCFG1_CFUNOPT 0x80
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#define BCFG1_CREQOPT 0x40
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#define BCFG1_DMA8 0x10
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@ -220,7 +220,7 @@
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#define BCFG1_MIOEN 0x02
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#define BCFG1_CISDLYEN 0x01
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// Bits in RAMBIST registers
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/* Bits in RAMBIST registers */
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#define BISTCMD_TSTPAT5 0x00
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#define BISTCMD_TSTPATA 0x80
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#define BISTCMD_TSTERR 0x20
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@ -236,7 +236,7 @@
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#define BISTSR2_CMDPRTEN 0x02
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#define BISTSR2_RAMTSTEN 0x01
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// Bits in the I2MCFG EEPROM register
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/* Bits in the I2MCFG EEPROM register */
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#define I2MCFG_BOUNDCTL 0x80
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#define I2MCFG_WAITCTL 0x20
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#define I2MCFG_SCLOECTL 0x10
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@ -245,28 +245,28 @@
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#define I2MCFG_I2MLDSEQ 0x02
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#define I2MCFG_I2CMFAST 0x01
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// Bits in the I2MCSR EEPROM register
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/* Bits in the I2MCSR EEPROM register */
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#define I2MCSR_EEMW 0x80
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#define I2MCSR_EEMR 0x40
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#define I2MCSR_AUTOLD 0x08
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#define I2MCSR_NACK 0x02
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#define I2MCSR_DONE 0x01
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// Bits in the PMC1 register
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/* Bits in the PMC1 register */
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#define SPS_RST 0x80
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#define PCISTIKY 0x40
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#define PME_OVR 0x02
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// Bits in the STICKYHW register
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/* Bits in the STICKYHW register */
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#define STICKHW_DS1_SHADOW 0x02
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#define STICKHW_DS0_SHADOW 0x01
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// Bits in the TMCTL register
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/* Bits in the TMCTL register */
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#define TMCTL_TSUSP 0x04
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#define TMCTL_TMD 0x02
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#define TMCTL_TE 0x01
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// Bits in the TFTCTL register
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/* Bits in the TFTCTL register */
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#define TFTCTL_HWUTSF 0x80
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#define TFTCTL_TBTTSYNC 0x40
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#define TFTCTL_HWUTSFEN 0x20
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@ -276,7 +276,7 @@
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#define TFTCTL_TSFCNTRST 0x02
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#define TFTCTL_TSFCNTREN 0x01
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// Bits in the EnhanceCFG register
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/* Bits in the EnhanceCFG register */
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#define EnCFG_BarkerPream 0x00020000
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#define EnCFG_NXTBTTCFPSTR 0x00010000
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#define EnCFG_BcnSusClr 0x00000200
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@ -290,10 +290,10 @@
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#define EnCFG_BBType_b 0x00000001
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#define EnCFG_BBType_a 0x00000000
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// Bits in the Page1Sel register
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/* Bits in the Page1Sel register */
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#define PAGE1_SEL 0x01
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// Bits in the CFG register
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/* Bits in the CFG register */
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#define CFG_TKIPOPT 0x80
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#define CFG_RXDMAOPT 0x40
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#define CFG_TMOT_SW 0x20
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@ -304,7 +304,7 @@
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#define CFG_NOTXTIMEOUT 0x02
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#define CFG_NOBUFOPT 0x01
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// Bits in the TEST register
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/* Bits in the TEST register */
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#define TEST_LBEXT 0x80
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#define TEST_LBINT 0x40
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#define TEST_LBNONE 0x00
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@ -315,7 +315,7 @@
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#define TEST_NOCTS 0x02
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#define TEST_NOACK 0x01
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// Bits in the HOSTCR register
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/* Bits in the HOSTCR register */
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#define HOSTCR_TXONST 0x80
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#define HOSTCR_RXONST 0x40
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#define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */
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@ -325,17 +325,17 @@
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#define HOSTCR_MACEN 0x02 /* 0000 0010 */
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#define HOSTCR_SOFTRST 0x01 /* 0000 0001 */
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// Bits in the MACCR register
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/* Bits in the MACCR register */
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#define MACCR_SYNCFLUSHOK 0x04
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#define MACCR_SYNCFLUSH 0x02
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#define MACCR_CLRNAV 0x01
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// Bits in the MAC_REG_GPIOCTL0 register
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/* Bits in the MAC_REG_GPIOCTL0 register */
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#define LED_ACTSET 0x01
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#define LED_RFOFF 0x02
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#define LED_NOCONNECT 0x04
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// Bits in the RCR register
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/* Bits in the RCR register */
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#define RCR_SSID 0x80
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#define RCR_RXALLTYPE 0x40
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#define RCR_UNICAST 0x20
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@ -345,11 +345,11 @@
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#define RCR_ERRCRC 0x02
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#define RCR_BSSID 0x01
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// Bits in the TCR register
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/* Bits in the TCR register */
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#define TCR_SYNCDCFOPT 0x02
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#define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */
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// Bits in the IMR register
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/* Bits in the IMR register */
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#define IMR_MEASURESTART 0x80000000
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#define IMR_QUIETSTART 0x20000000
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#define IMR_RADARDETECT 0x10000000
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@ -369,7 +369,7 @@
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#define IMR_AC0DMA 0x00000002
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#define IMR_TXDMA0 0x00000001
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// Bits in the ISR register
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/* Bits in the ISR register */
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#define ISR_MEASURESTART 0x80000000
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#define ISR_QUIETSTART 0x20000000
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#define ISR_RADARDETECT 0x10000000
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@ -389,7 +389,7 @@
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#define ISR_AC0DMA 0x00000002
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#define ISR_TXDMA0 0x00000001
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// Bits in the PSCFG register
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/* Bits in the PSCFG register */
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#define PSCFG_PHILIPMD 0x40
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#define PSCFG_WAKECALEN 0x20
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#define PSCFG_WAKETMREN 0x10
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@ -398,7 +398,7 @@
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#define PSCFG_SLEEPSYN 0x02
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#define PSCFG_AUTOSLEEP 0x01
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// Bits in the PSCTL register
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/* Bits in the PSCTL register */
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#define PSCTL_WAKEDONE 0x20
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#define PSCTL_PS 0x10
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#define PSCTL_GO2DOZE 0x08
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@ -406,7 +406,7 @@
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#define PSCTL_ALBCN 0x02
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#define PSCTL_PSEN 0x01
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// Bits in the PSPWSIG register
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/* Bits in the PSPWSIG register */
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#define PSSIG_WPE3 0x80
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#define PSSIG_WPE2 0x40
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#define PSSIG_WPE1 0x20
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@ -416,17 +416,17 @@
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#define PSSIG_SPE1 0x02
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#define PSSIG_SRADIOPE 0x01
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// Bits in the BBREGCTL register
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/* Bits in the BBREGCTL register */
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#define BBREGCTL_DONE 0x04
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#define BBREGCTL_REGR 0x02
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#define BBREGCTL_REGW 0x01
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// Bits in the IFREGCTL register
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/* Bits in the IFREGCTL register */
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#define IFREGCTL_DONE 0x04
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#define IFREGCTL_IFRF 0x02
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#define IFREGCTL_REGW 0x01
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// Bits in the SOFTPWRCTL register
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/* Bits in the SOFTPWRCTL register */
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#define SOFTPWRCTL_RFLEOPT 0x0800
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#define SOFTPWRCTL_TXPEINV 0x0200
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#define SOFTPWRCTL_SWPECTI 0x0100
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@ -437,63 +437,63 @@
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#define SOFTPWRCTL_SWPE1 0x0002
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#define SOFTPWRCTL_SWPE3 0x0001
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// Bits in the GPIOCTL1 register
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/* Bits in the GPIOCTL1 register */
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#define GPIO1_DATA1 0x20
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#define GPIO1_MD1 0x10
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#define GPIO1_DATA0 0x02
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#define GPIO1_MD0 0x01
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// Bits in the DMACTL register
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/* Bits in the DMACTL register */
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#define DMACTL_CLRRUN 0x00080000
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#define DMACTL_RUN 0x00000008
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#define DMACTL_WAKE 0x00000004
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#define DMACTL_DEAD 0x00000002
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#define DMACTL_ACTIVE 0x00000001
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// Bits in the RXDMACTL0 register
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/* Bits in the RXDMACTL0 register */
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#define RX_PERPKT 0x00000100
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#define RX_PERPKTCLR 0x01000000
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// Bits in the BCNDMACTL register
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/* Bits in the BCNDMACTL register */
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#define BEACON_READY 0x01
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// Bits in the MISCFFCTL register
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/* Bits in the MISCFFCTL register */
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#define MISCFFCTL_WRITE 0x0001
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// Bits in WAKEUPEN0
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/* Bits in WAKEUPEN0 */
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#define WAKEUPEN0_DIRPKT 0x10
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#define WAKEUPEN0_LINKOFF 0x08
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#define WAKEUPEN0_ATIMEN 0x04
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#define WAKEUPEN0_TIMEN 0x02
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#define WAKEUPEN0_MAGICEN 0x01
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// Bits in WAKEUPEN1
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/* Bits in WAKEUPEN1 */
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#define WAKEUPEN1_128_3 0x08
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#define WAKEUPEN1_128_2 0x04
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#define WAKEUPEN1_128_1 0x02
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#define WAKEUPEN1_128_0 0x01
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// Bits in WAKEUPSR0
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/* Bits in WAKEUPSR0 */
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#define WAKEUPSR0_DIRPKT 0x10
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#define WAKEUPSR0_LINKOFF 0x08
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#define WAKEUPSR0_ATIMEN 0x04
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#define WAKEUPSR0_TIMEN 0x02
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#define WAKEUPSR0_MAGICEN 0x01
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// Bits in WAKEUPSR1
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/* Bits in WAKEUPSR1 */
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#define WAKEUPSR1_128_3 0x08
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#define WAKEUPSR1_128_2 0x04
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#define WAKEUPSR1_128_1 0x02
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#define WAKEUPSR1_128_0 0x01
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// Bits in the MAC_REG_GPIOCTL register
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/* Bits in the MAC_REG_GPIOCTL register */
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#define GPIO0_MD 0x01
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#define GPIO0_DATA 0x02
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#define GPIO0_INTMD 0x04
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#define GPIO1_MD 0x10
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#define GPIO1_DATA 0x20
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// Bits in the MSRCTL register
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/* Bits in the MSRCTL register */
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#define MSRCTL_FINISH 0x80
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#define MSRCTL_READY 0x40
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#define MSRCTL_RADARDETECT 0x20
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@ -503,26 +503,26 @@
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#define MSRCTL_QUIETINT 0x02
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#define MSRCTL_QUIETEN 0x01
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// Bits in the MSRCTL1 register
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/* Bits in the MSRCTL1 register */
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#define MSRCTL1_TXPWR 0x08
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#define MSRCTL1_CSAPAREN 0x04
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#define MSRCTL1_TXPAUSE 0x01
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// Loopback mode
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/* Loopback mode */
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#define MAC_LB_EXT 0x02
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#define MAC_LB_INTERNAL 0x01
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#define MAC_LB_NONE 0x00
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#define Default_BI 0x200
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// MiscFIFO Offset
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/* MiscFIFO Offset */
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#define MISCFIFO_KEYETRY0 32
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#define MISCFIFO_KEYENTRYSIZE 22
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#define MISCFIFO_SYNINFO_IDX 10
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#define MISCFIFO_SYNDATA_IDX 11
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#define MISCFIFO_SYNDATASIZE 21
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// enabled mask value of irq
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/* enabled mask value of irq */
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#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
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IMR_RXDMA1 | \
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IMR_RXNOBUF | \
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@ -538,13 +538,13 @@
|
|||
IMR_AC0DMA | \
|
||||
IMR_TXDMA0)
|
||||
|
||||
// max time out delay time
|
||||
/* max time out delay time */
|
||||
#define W_MAX_TIMEOUT 0xFFF0U
|
||||
|
||||
// wait time within loop
|
||||
/* wait time within loop */
|
||||
#define CB_DELAY_LOOP_WAIT 10 /* 10ms */
|
||||
|
||||
// revision id
|
||||
/* revision id */
|
||||
#define REV_ID_VT3253_A0 0x00
|
||||
#define REV_ID_VT3253_A1 0x01
|
||||
#define REV_ID_VT3253_B0 0x08
|
||||
|
|
@ -628,12 +628,12 @@ do { \
|
|||
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
// set the chip with current BCN tx descriptor address
|
||||
/* set the chip with current BCN tx descriptor address */
|
||||
#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
|
||||
dwCurrDescAddr)
|
||||
|
||||
// set the chip with current BCN length
|
||||
/* set the chip with current BCN length */
|
||||
#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
|
||||
wCurrBCNLength)
|
||||
|
|
|
|||
Loading…
Reference in New Issue