dmaengine: sun6i: Add support for Allwinner A64 and compatibles
The A64 SoC has the same dma engine as the H3 (sun8i), with a reduced amount of physical channels. To allow future reuse of the compatible, leave the channel count etc. in the config data blank and retrieve it from the devicetree. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>hifive-unleashed-5.1
parent
d93cc0e788
commit
12e0177055
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@ -1121,6 +1121,25 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
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};
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/*
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* The A64 binding uses the number of dma channels from the
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* device tree node.
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*/
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static struct sun6i_dma_config sun50i_a64_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
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.set_burst_length = sun6i_set_burst_length_h3,
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.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
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.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
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};
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/*
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* The V3s have only 8 physical channels, a maximum DRQ port id of 23,
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* and a total of 24 usable source and destination endpoints.
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@ -1148,6 +1167,7 @@ static const struct of_device_id sun6i_dma_match[] = {
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{ .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
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{ .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
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{ .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
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{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sun6i_dma_match);
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