spi: stm32: FIFO threshold level - fix align packet size
commit5.4-rM2-2.2.x-imx-squasheda590370d91
upstream. if cur_bpw <= 8 and xfer_len < 4 then the value of fthlv will be 1 and SPI registers content may have been lost. * If SPI data register is accessed as a 16-bit register and DSIZE <= 8bit, better to select FTHLV = 2, 4, 6 etc * If SPI data register is accessed as a 32-bit register and DSIZE > 8bit, better to select FTHLV = 2, 4, 6 etc, while if DSIZE <= 8bit, better to select FTHLV = 4, 8, 12 etc Signed-off-by: Roman Guskov <rguskov@dh-electronics.com> Fixes:dcbe0d84df
("spi: add driver for STM32 SPI controller") Reviewed-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20201221123532.27272-1-rguskov@dh-electronics.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -494,9 +494,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
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/* align packet size with data registers access */
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/* align packet size with data registers access */
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if (spi->cur_bpw > 8)
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if (spi->cur_bpw > 8)
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fthlv -= (fthlv % 2); /* multiple of 2 */
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fthlv += (fthlv % 2) ? 1 : 0;
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else
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else
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fthlv -= (fthlv % 4); /* multiple of 4 */
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fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
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if (!fthlv)
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if (!fthlv)
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fthlv = 1;
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fthlv = 1;
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