net: dsa: bcm_sf2: add HW bridging support
Implement the bridge join, leave and set_stp callbacks by making that we do the following: - when a port joins the bridge, all existing ports in the bridge get their VLAN control register updated with that joining port - the joining port is including all existing bridge ports in its own VLAN control register The leave operation is fairly similar, special care must be taken to make sure that port leaving the bridging is not removing itself from its own VLAN control register. Since the various BR_* states apply directly to our HW semantics, we just need to translate these constants into their corresponding HW settings, and voila! We make sure to trigger a fast-ageing process for ports that are joining/leaving the bridge and transition from incompatible states, this is equivalent to triggering an ARL flush for that port. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
b73adef677
commit
12f460f234
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@ -23,6 +23,7 @@
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#include <linux/of_address.h>
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#include <net/dsa.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include "bcm_sf2.h"
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#include "bcm_sf2_regs.h"
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@ -299,10 +300,14 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
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if (port == 7)
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intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
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/* Set this port, and only this one to be in the default VLAN */
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/* Set this port, and only this one to be in the default VLAN,
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* if member of a bridge, restore its membership prior to
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* bringing down this port.
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*/
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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reg &= ~PORT_VLAN_CTRL_MASK;
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reg |= (1 << port);
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reg |= priv->port_sts[port].vlan_ctl_mask;
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
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bcm_sf2_imp_vlan_setup(ds, cpu_port);
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@ -400,6 +405,151 @@ static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
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return 0;
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}
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/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
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* flush for that port.
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*/
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static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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unsigned int timeout = 1000;
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u32 reg;
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core_writel(priv, port, CORE_FAST_AGE_PORT);
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reg = core_readl(priv, CORE_FAST_AGE_CTRL);
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reg |= EN_AGE_PORT | FAST_AGE_STR_DONE;
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core_writel(priv, reg, CORE_FAST_AGE_CTRL);
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do {
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reg = core_readl(priv, CORE_FAST_AGE_CTRL);
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if (!(reg & FAST_AGE_STR_DONE))
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break;
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cpu_relax();
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} while (timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
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u32 br_port_mask)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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unsigned int i;
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u32 reg, p_ctl;
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p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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for (i = 0; i < priv->hw_params.num_ports; i++) {
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if (!((1 << i) & br_port_mask))
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continue;
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/* Add this local port to the remote port VLAN control
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* membership and update the remote port bitmask
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*/
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
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reg |= 1 << port;
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
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priv->port_sts[i].vlan_ctl_mask = reg;
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p_ctl |= 1 << i;
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}
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/* Configure the local port VLAN control membership to include
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* remote ports and update the local port bitmask
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*/
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core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
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priv->port_sts[port].vlan_ctl_mask = p_ctl;
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return 0;
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}
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static int bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
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u32 br_port_mask)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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unsigned int i;
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u32 reg, p_ctl;
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p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
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for (i = 0; i < priv->hw_params.num_ports; i++) {
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/* Don't touch the remaining ports */
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if (!((1 << i) & br_port_mask))
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continue;
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reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
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reg &= ~(1 << port);
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core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
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priv->port_sts[port].vlan_ctl_mask = reg;
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/* Prevent self removal to preserve isolation */
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if (port != i)
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p_ctl &= ~(1 << i);
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}
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core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
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priv->port_sts[port].vlan_ctl_mask = p_ctl;
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return 0;
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}
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static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
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u8 state)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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u8 hw_state, cur_hw_state;
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int ret = 0;
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u32 reg;
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reg = core_readl(priv, CORE_G_PCTL_PORT(port));
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cur_hw_state = reg >> G_MISTP_STATE_SHIFT;
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switch (state) {
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case BR_STATE_DISABLED:
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hw_state = G_MISTP_DIS_STATE;
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break;
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case BR_STATE_LISTENING:
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hw_state = G_MISTP_LISTEN_STATE;
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break;
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case BR_STATE_LEARNING:
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hw_state = G_MISTP_LEARN_STATE;
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break;
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case BR_STATE_FORWARDING:
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hw_state = G_MISTP_FWD_STATE;
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break;
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case BR_STATE_BLOCKING:
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hw_state = G_MISTP_BLOCK_STATE;
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break;
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default:
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pr_err("%s: invalid STP state: %d\n", __func__, state);
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return -EINVAL;
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}
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/* Fast-age ARL entries if we are moving a port from Learning or
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* Forwarding state to Disabled, Blocking or Listening state
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*/
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if (cur_hw_state != hw_state) {
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if (cur_hw_state & 4 && !(hw_state & 4)) {
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ret = bcm_sf2_sw_fast_age_port(ds, port);
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if (ret) {
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pr_err("%s: fast-ageing failed\n", __func__);
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return ret;
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}
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}
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}
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reg = core_readl(priv, CORE_G_PCTL_PORT(port));
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reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
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reg |= hw_state;
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core_writel(priv, reg, CORE_G_PCTL_PORT(port));
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return 0;
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}
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static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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@ -916,6 +1066,9 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = {
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.port_disable = bcm_sf2_port_disable,
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.get_eee = bcm_sf2_sw_get_eee,
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.set_eee = bcm_sf2_sw_set_eee,
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.port_join_bridge = bcm_sf2_sw_br_join,
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.port_leave_bridge = bcm_sf2_sw_br_leave,
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.port_stp_update = bcm_sf2_sw_br_set_stp_state,
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};
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static int __init bcm_sf2_init(void)
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@ -46,6 +46,8 @@ struct bcm_sf2_port_status {
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unsigned int link;
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struct ethtool_eee eee;
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u32 vlan_ctl_mask;
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};
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struct bcm_sf2_priv {
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@ -163,6 +163,21 @@
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#define EN_CHIP_RST (1 << 6)
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#define EN_SW_RESET (1 << 4)
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#define CORE_FAST_AGE_CTRL 0x00220
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#define EN_FAST_AGE_STATIC (1 << 0)
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#define EN_AGE_DYNAMIC (1 << 1)
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#define EN_AGE_PORT (1 << 2)
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#define EN_AGE_VLAN (1 << 3)
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#define EN_AGE_SPT (1 << 4)
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#define EN_AGE_MCAST (1 << 5)
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#define FAST_AGE_STR_DONE (1 << 7)
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#define CORE_FAST_AGE_PORT 0x00224
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#define AGE_PORT_MASK 0xf
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#define CORE_FAST_AGE_VID 0x00228
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#define AGE_VID_MASK 0x3fff
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#define CORE_LNKSTS 0x00400
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#define LNK_STS_MASK 0x1ff
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