ARM: SoC platform updates for v4.5
Updates for new platform support: - New platform: Tango4 from Sigma Designs. - Broadcom BCM2836 (Raspberry Pi 2 SoC) - Enable cpufreq on Freescale i.MX7D - Rockchip: SMP support for rk3036, general support for rk3228 - SMP support on Broadcom Kona and NSP - Cleanups for OMAP removing legacy IOMMU data + a bunch of misc fixes and tweaks for various platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWnrvIAAoJEIwa5zzehBx3j0oP/i1WKGraSHS/w29ms4vfisFW bteUAsgh9aG8GCp/kigjmdMbWMdCRQfXp4D+o+SSr2DcM0q2iZzXV2WTeQ6YPAJM Fn431nuPn37ULd9PXdEhgiTDfDmVpvZrHeIQpDxC/TccRj4hkbxkMn6+s5WGkJLR DAr3h2mjKgulKZ4Wlj30rOxTDO9kVqTTIxjZXhbmMxepgMihSpvRGMXbKjxVHDSe NdCoIlfjhu6trr9d39b3POQVDCtrr82WvgrlfrhZZW6YXq7dIb3hhM1RldHCM+a7 mnNDMoVDCEjLM7WLkgoOzsX4j+MyCbrsBY9DV9Zs7MtntWGcD+oH0M+ZLjrtlPef vebi+yBh/JH9fyrOiusSzbRaimy5o/NO/tYFgEAh/zk6GhwJwBYBvM1nexnfSHhv LMY+nSrgZYdN9qHurwjaBmAAmp8u0XZIz/MLQA4WpoqqoAcV2X3gtMcQMdL+nio5 sUlE60/BcXjHqp/gt3MblxZy2WVzklCuqprOSYxhPwFDx7i9SKb9erSyzEkmzQDP UU+8Bory8egR537GaxM+izq9LQ3HLpWnyGPXSGx1s0vzNpZTsYC49eFK44vJRtLK QOlFG1VAupFP5S7kDneXJ8KoWcOwG3OccPfPTvyaC8SIezjXrKDgISV2mHOghYlk uNYO2fcyBoUX9jG3dUy8 =FP4V -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Updates for new platform support: - New platform: Tango4 from Sigma Designs. - Broadcom BCM2836 (Raspberry Pi 2 SoC) - Enable cpufreq on Freescale i.MX7D - Rockchip: SMP support for rk3036, general support for rk3228 - SMP support on Broadcom Kona and NSP - Cleanups for OMAP removing legacy IOMMU data + a bunch of misc fixes and tweaks for various platforms" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (46 commits) ARM: tango: Fix UP build issues ARM: tango: pass ARM arch level for smc.S ARM: bcm2835: Add Kconfig support for bcm2836 ARM: OMAP2+: Add support for dm814x and dra62x usb ARM: OMAP2+: Add mmc hwmod entries for dm814x ARM: OMAP2+: Update 81xx clock and power domains for default, active and sgx ARM: OMAP2+: Fix SoC detection for dra62x j5-eco ARM: tango4: Initial platform support ARM: bcm2835: Add a compat string for bcm2836 machine probe dt-bindings: Add root properties for Raspberry Pi 2 ARM: imx: select SRC for i.MX7 ARM: uniphier: select PINCTRL ARM: OMAP2+: Remove device creation for omap-pcm-audio ARM: OMAP1: Remove device creation for omap-pcm-audio ARM: rockchip: enable support for RK3228 SoCs ARM: rockchip: use const and __initconst for rk3036 smp_operations ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER ARM: BCM: Add SMP support for Broadcom 4708 ARM: BCM: Add SMP support for Broadcom NSP ARM: BCM: Clean up SMP support for Broadcom Kona ...hifive-unleashed-5.1
Linus Torvalds
commit
1305eda751
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@ -26,6 +26,10 @@ Raspberry Pi Model B+
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Required root node properties:
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compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
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Raspberry Pi 2 Model B
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Required root node properties:
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compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
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Raspberry Pi Compute Module
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Required root node properties:
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compatible = "raspberrypi,compute-module", "brcm,bcm2835";
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@ -202,6 +202,7 @@ nodes to be present and contain the properties described below.
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"rockchip,rk3036-smp"
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"rockchip,rk3066-smp"
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"ste,dbx500-smp"
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@ -1602,6 +1602,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git
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N: stm32
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F: drivers/clocksource/armv7m_systick.c
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ARM/TANGO ARCHITECTURE
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M: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: arch/arm/mach-tango/
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F: arch/arm/boot/dts/tango*
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ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -831,6 +831,8 @@ source "arch/arm/mach-sunxi/Kconfig"
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source "arch/arm/mach-prima2/Kconfig"
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source "arch/arm/mach-tango/Kconfig"
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source "arch/arm/mach-tegra/Kconfig"
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source "arch/arm/mach-u300/Kconfig"
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@ -129,7 +129,12 @@ choice
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config DEBUG_BCM2835
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bool "Kernel low-level debugging on BCM2835 PL011 UART"
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depends on ARCH_BCM2835
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depends on ARCH_BCM2835 && ARCH_MULTI_V6
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select DEBUG_UART_PL01X
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config DEBUG_BCM2836
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bool "Kernel low-level debugging on BCM2836 PL011 UART"
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depends on ARCH_BCM2835 && ARCH_MULTI_V7
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select DEBUG_UART_PL01X
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config DEBUG_BCM_5301X
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@ -1461,6 +1466,7 @@ config DEBUG_UART_PHYS
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default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
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default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
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default 0x20201000 if DEBUG_BCM2835
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default 0x3f201000 if DEBUG_BCM2836
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default 0x3e000000 if DEBUG_BCM_KONA_UART
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default 0x4000e400 if DEBUG_LL_UART_EFM32
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default 0x40081000 if DEBUG_LPC18XX_UART0
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@ -1547,7 +1553,7 @@ config DEBUG_UART_VIRT
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default 0xf0000be0 if ARCH_EBSA110
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default 0xf0010000 if DEBUG_ASM9260_UART
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default 0xf01fb000 if DEBUG_NOMADIK_UART
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default 0xf0201000 if DEBUG_BCM2835
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default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
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default 0xf1000300 if DEBUG_BCM_5301X
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default 0xf1002000 if DEBUG_MT8127_UART0
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default 0xf1006000 if DEBUG_MT6589_UART0
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@ -211,6 +211,7 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
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machine-$(CONFIG_ARCH_STI) += sti
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machine-$(CONFIG_ARCH_STM32) += stm32
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machine-$(CONFIG_ARCH_SUNXI) += sunxi
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machine-$(CONFIG_ARCH_TANGO) += tango
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machine-$(CONFIG_ARCH_TEGRA) += tegra
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machine-$(CONFIG_ARCH_U300) += u300
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machine-$(CONFIG_ARCH_U8500) += ux500
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@ -31,7 +31,6 @@
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x3500417c>;
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cpu0: cpu@0 {
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device_type = "cpu";
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@ -42,6 +41,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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secondary-boot-reg = <0x3500417c>;
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reg = <1>;
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};
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};
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@ -31,7 +31,6 @@
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x35004178>;
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cpu0: cpu@0 {
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device_type = "cpu";
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@ -42,6 +41,7 @@
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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secondary-boot-reg = <0x35004178>;
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reg = <1>;
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};
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};
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@ -15,6 +15,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm-nsp-smp";
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cpu@0 {
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device_type = "cpu";
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@ -27,6 +28,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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secondary-boot-reg = <0xffff0400>;
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reg = <0x1>;
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};
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};
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@ -152,6 +152,20 @@
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interrupt-parent = <&gic>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* Reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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mipi_phy: video-phy@10020710 {
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compatible = "samsung,s5pv210-mipi-video-phy";
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#phy-cells = <1>;
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@ -158,6 +158,20 @@
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interrupt-parent = <&gic>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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dsi_0: dsi@11C80000 {
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compatible = "samsung,exynos4210-mipi-dsi";
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reg = <0x11C80000 0x10000>;
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@ -88,6 +88,20 @@
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status = "disabled";
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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fimd: fimd@14400000 {
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compatible = "samsung,exynos5250-fimd";
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interrupt-parent = <&combiner>;
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@ -102,6 +102,20 @@
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reg = <0x10040000 0x5000>;
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};
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poweroff: syscon-poweroff {
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compatible = "syscon-poweroff";
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regmap = <&pmu_system_controller>;
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offset = <0x330C>; /* PS_HOLD_CONTROL */
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mask = <0x5200>; /* reset value */
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pmu_system_controller>;
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offset = <0x0400>; /* SWRESET */
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mask = <0x1>;
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};
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mct: mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0xB00>;
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@ -43,6 +43,8 @@ config ARCH_BCM_NSP
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select ARCH_BCM_IPROC
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select ARM_ERRATA_764369 if SMP
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select HAVE_SMP
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help
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Support for Broadcom Northstar Plus SoC.
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Broadcom Northstar Plus family of SoCs are used for switching control
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@ -56,6 +58,11 @@ config ARCH_BCM_5301X
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bool "Broadcom BCM470X / BCM5301X ARM SoC"
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depends on ARCH_MULTI_V7
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select ARCH_BCM_IPROC
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select ARM_ERRATA_754322
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select ARM_ERRATA_775420
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select ARM_ERRATA_764369 if SMP
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select HAVE_SMP
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help
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Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
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@ -129,17 +136,18 @@ comment "Other Architectures"
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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depends on ARCH_MULTI_V6
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depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select ARM_AMBA
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select ARM_ERRATA_411920
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select ARM_ERRATA_411920 if ARCH_MULTI_V6
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select ARM_TIMER_SP804
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select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
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select CLKSRC_OF
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select PINCTRL
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select PINCTRL_BCM2835
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help
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This enables support for the Broadcom BCM2835 SoC. This SoC is
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used in the Raspberry Pi and Roku 2 devices.
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This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
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This SoC is used in the Raspberry Pi and Roku 2 devices.
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config ARCH_BCM_63XX
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bool "Broadcom BCM63xx DSL SoC"
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@ -14,7 +14,11 @@
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
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# Northstar Plus
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obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
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obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
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ifeq ($(CONFIG_ARCH_BCM_NSP),y)
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obj-$(CONFIG_SMP) += platsmp.o
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endif
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# BCM281XX
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obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
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@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
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obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
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# BCM281XX and BCM21664 SMP support
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obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
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obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
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# BCM281XX and BCM21664 L2 cache control
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obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
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@ -39,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
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# BCM5301X
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obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
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ifeq ($(CONFIG_ARCH_BCM_5301X),y)
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obj-$(CONFIG_SMP) += platsmp.o
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endif
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# BCM63XXx
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ifeq ($(CONFIG_ARCH_BCM_63XX),y)
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@ -9,40 +9,6 @@
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/siginfo.h>
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#include <asm/signal.h>
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static bool first_fault = true;
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static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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if ((fsr == 0x1406 || fsr == 0x1c06) && first_fault) {
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first_fault = false;
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/*
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* These faults with codes 0x1406 (BCM4709) or 0x1c06 happens
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* for no good reason, possibly left over from the CFE boot
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* loader.
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*/
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pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
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addr, fsr);
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/* Returning non-zero causes fault display and panic */
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return 0;
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}
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/* Others should cause a fault */
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return 1;
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}
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static void __init bcm5301x_init_early(void)
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{
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/* Install our hook */
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hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
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"imprecise external abort");
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}
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static const char *const bcm5301x_dt_compat[] __initconst = {
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"brcm,bcm4708",
|
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@ -52,6 +18,5 @@ static const char *const bcm5301x_dt_compat[] __initconst = {
|
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DT_MACHINE_START(BCM5301X, "BCM5301X")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
|
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.init_early = bcm5301x_init_early,
|
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.dt_compat = bcm5301x_dt_compat,
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MACHINE_END
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@ -36,7 +36,12 @@ static void __init bcm2835_init(void)
|
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}
|
||||
|
||||
static const char * const bcm2835_compat[] = {
|
||||
#ifdef CONFIG_ARCH_MULTI_V6
|
||||
"brcm,bcm2835",
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_MULTI_V7
|
||||
"brcm,bcm2836",
|
||||
#endif
|
||||
NULL
|
||||
};
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||||
|
||||
|
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|
|||
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@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Broadcom Corporation
|
||||
* Copyright (C) 2014-2015 Broadcom Corporation
|
||||
* Copyright 2014 Linaro Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -12,12 +12,17 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
|
@ -30,9 +35,10 @@
|
|||
|
||||
/* Name of device node property defining secondary boot register location */
|
||||
#define OF_SECONDARY_BOOT "secondary-boot-reg"
|
||||
#define MPIDR_CPUID_BITMASK 0x3
|
||||
|
||||
/* I/O address of register used to coordinate secondary core startup */
|
||||
static u32 secondary_boot;
|
||||
static u32 secondary_boot_addr;
|
||||
|
||||
/*
|
||||
* Enable the Cortex A9 Snoop Control Unit
|
||||
|
|
@ -75,47 +81,101 @@ static int __init scu_a9_enable(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int nsp_write_lut(void)
|
||||
{
|
||||
void __iomem *sku_rom_lut;
|
||||
phys_addr_t secondary_startup_phy;
|
||||
|
||||
if (!secondary_boot_addr) {
|
||||
pr_warn("required secondary boot register not specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
|
||||
sizeof(secondary_boot_addr));
|
||||
if (!sku_rom_lut) {
|
||||
pr_warn("unable to ioremap SKU-ROM LUT register\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
secondary_startup_phy = virt_to_phys(secondary_startup);
|
||||
BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
|
||||
|
||||
writel_relaxed(secondary_startup_phy, sku_rom_lut);
|
||||
|
||||
/* Ensure the write is visible to the secondary core */
|
||||
smp_wmb();
|
||||
|
||||
iounmap(sku_rom_lut);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
|
||||
struct device_node *node;
|
||||
struct device_node *cpus_node = NULL;
|
||||
struct device_node *cpu_node = NULL;
|
||||
int ret;
|
||||
|
||||
BUG_ON(secondary_boot); /* We're called only once */
|
||||
|
||||
/*
|
||||
* This function is only called via smp_ops->smp_prepare_cpu().
|
||||
* That only happens if a "/cpus" device tree node exists
|
||||
* and has an "enable-method" property that selects the SMP
|
||||
* operations defined herein.
|
||||
*/
|
||||
node = of_find_node_by_path("/cpus");
|
||||
BUG_ON(!node);
|
||||
cpus_node = of_find_node_by_path("/cpus");
|
||||
if (!cpus_node)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Our secondary enable method requires a "secondary-boot-reg"
|
||||
* property to specify a register address used to request the
|
||||
* ROM code boot a secondary code. If we have any trouble
|
||||
* getting this we fall back to uniprocessor mode.
|
||||
*/
|
||||
if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
|
||||
pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
|
||||
node->name);
|
||||
ret = -ENOENT; /* Arrange to disable SMP */
|
||||
goto out;
|
||||
for_each_child_of_node(cpus_node, cpu_node) {
|
||||
u32 cpuid;
|
||||
|
||||
if (of_node_cmp(cpu_node->type, "cpu"))
|
||||
continue;
|
||||
|
||||
if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
|
||||
pr_debug("%s: missing reg property\n",
|
||||
cpu_node->full_name);
|
||||
ret = -ENOENT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* "secondary-boot-reg" property should be defined only
|
||||
* for secondary cpu
|
||||
*/
|
||||
if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
|
||||
/*
|
||||
* Our secondary enable method requires a
|
||||
* "secondary-boot-reg" property to specify a register
|
||||
* address used to request the ROM code boot a secondary
|
||||
* core. If we have any trouble getting this we fall
|
||||
* back to uniprocessor mode.
|
||||
*/
|
||||
if (of_property_read_u32(cpu_node,
|
||||
OF_SECONDARY_BOOT,
|
||||
&secondary_boot_addr)) {
|
||||
pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
|
||||
cpu_node->name);
|
||||
ret = -ENOENT;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
|
||||
* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
|
||||
* returned, the SoC reported a uniprocessor configuration.
|
||||
* We bail on any other error.
|
||||
*/
|
||||
ret = scu_a9_enable();
|
||||
out:
|
||||
of_node_put(node);
|
||||
of_node_put(cpu_node);
|
||||
of_node_put(cpus_node);
|
||||
|
||||
if (ret) {
|
||||
/* Update the CPU present map to reflect uniprocessor mode */
|
||||
BUG_ON(ret != -ENOENT);
|
||||
pr_warn("disabling SMP\n");
|
||||
init_cpu_present(&only_cpu_0);
|
||||
}
|
||||
|
|
@ -139,7 +199,7 @@ out:
|
|||
* - Wait for the secondary boot register to be re-written, which
|
||||
* indicates the secondary core has started.
|
||||
*/
|
||||
static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
void __iomem *boot_reg;
|
||||
phys_addr_t boot_func;
|
||||
|
|
@ -154,15 +214,16 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!secondary_boot) {
|
||||
if (!secondary_boot_addr) {
|
||||
pr_err("required secondary boot register not specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
|
||||
boot_reg = ioremap_nocache(
|
||||
(phys_addr_t)secondary_boot_addr, sizeof(u32));
|
||||
if (!boot_reg) {
|
||||
pr_err("unable to map boot register for cpu %u\n", cpu_id);
|
||||
return -ENOSYS;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -191,12 +252,39 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
|
||||
pr_err("timeout waiting for cpu %u to start\n", cpu_id);
|
||||
|
||||
return -ENOSYS;
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* After wake up, secondary core branches to the startup
|
||||
* address programmed at SKU ROM LUT location.
|
||||
*/
|
||||
ret = nsp_write_lut();
|
||||
if (ret) {
|
||||
pr_err("unable to write startup addr to SKU ROM LUT\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Send a CPU wakeup interrupt to the secondary core */
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct smp_operations bcm_smp_ops __initconst = {
|
||||
.smp_prepare_cpus = bcm_smp_prepare_cpus,
|
||||
.smp_boot_secondary = bcm_boot_secondary,
|
||||
.smp_boot_secondary = kona_boot_secondary,
|
||||
};
|
||||
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
|
||||
&bcm_smp_ops);
|
||||
|
||||
struct smp_operations nsp_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = bcm_smp_prepare_cpus,
|
||||
.smp_boot_secondary = nsp_boot_secondary,
|
||||
};
|
||||
CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
|
||||
|
|
@ -29,6 +29,9 @@ menuconfig ARCH_EXYNOS
|
|||
select THERMAL
|
||||
select MFD_SYSCON
|
||||
select CLKSRC_EXYNOS_MCT
|
||||
select POWER_RESET
|
||||
select POWER_RESET_SYSCON
|
||||
select POWER_RESET_SYSCON_POWEROFF
|
||||
help
|
||||
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
|
||||
|
||||
|
|
|
|||
|
|
@ -14,9 +14,8 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#include "exynos-pmu.h"
|
||||
#include "regs-pmu.h"
|
||||
|
|
@ -681,23 +680,6 @@ static unsigned int const exynos5420_list_disable_pmu_reg[] = {
|
|||
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
|
||||
};
|
||||
|
||||
static void exynos_power_off(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
pr_info("Power down.\n");
|
||||
tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
|
||||
tmp ^= (1 << 8);
|
||||
pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
|
||||
|
||||
/* Wait a little so we don't give a false warning below */
|
||||
mdelay(100);
|
||||
|
||||
pr_err("Power down failed, please power off system manually.\n");
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
static void exynos5420_powerdown_conf(enum sys_powerdown mode)
|
||||
{
|
||||
u32 this_cluster;
|
||||
|
|
@ -879,14 +861,6 @@ static void exynos5420_pmu_init(void)
|
|||
pr_info("EXYNOS5420 PMU initialized\n");
|
||||
}
|
||||
|
||||
static int pmu_restart_notify(struct notifier_block *this,
|
||||
unsigned long code, void *unused)
|
||||
{
|
||||
pmu_raw_writel(0x1, EXYNOS_SWRESET);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static const struct exynos_pmu_data exynos3250_pmu_data = {
|
||||
.pmu_config = exynos3250_pmu_config,
|
||||
.pmu_init = exynos3250_pmu_init,
|
||||
|
|
@ -912,7 +886,7 @@ static const struct exynos_pmu_data exynos5250_pmu_data = {
|
|||
.powerdown_conf = exynos5_powerdown_conf,
|
||||
};
|
||||
|
||||
static struct exynos_pmu_data exynos5420_pmu_data = {
|
||||
static const struct exynos_pmu_data exynos5420_pmu_data = {
|
||||
.pmu_config = exynos5420_pmu_config,
|
||||
.pmu_init = exynos5420_pmu_init,
|
||||
.powerdown_conf = exynos5420_powerdown_conf,
|
||||
|
|
@ -944,20 +918,11 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = {
|
|||
{ /*sentinel*/ },
|
||||
};
|
||||
|
||||
/*
|
||||
* Exynos PMU restart notifier, handles restart functionality
|
||||
*/
|
||||
static struct notifier_block pmu_restart_handler = {
|
||||
.notifier_call = pmu_restart_notify,
|
||||
.priority = 128,
|
||||
};
|
||||
|
||||
static int exynos_pmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
pmu_base_addr = devm_ioremap_resource(dev, res);
|
||||
|
|
@ -982,12 +947,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, pmu_context);
|
||||
|
||||
ret = register_restart_handler(&pmu_restart_handler);
|
||||
if (ret)
|
||||
dev_warn(dev, "can't register restart handler err=%d\n", ret);
|
||||
|
||||
pm_power_off = exynos_power_off;
|
||||
|
||||
dev_dbg(dev, "Exynos PMU Driver probe done\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -484,15 +484,6 @@
|
|||
|
||||
#define EXYNOS5420_SWRESET_KFC_SEL 0x3
|
||||
|
||||
#include <asm/cputype.h>
|
||||
#define MAX_CPUS_IN_CLUSTER 4
|
||||
|
||||
static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
|
||||
{
|
||||
return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
|
||||
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
|
||||
}
|
||||
|
||||
/* Only for EXYNOS5420 */
|
||||
#define EXYNOS5420_ISP_ARM_OPTION 0x2488
|
||||
#define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3)
|
||||
|
|
|
|||
|
|
@ -563,6 +563,7 @@ config SOC_IMX7D
|
|||
select ARM_GIC
|
||||
select HAVE_IMX_ANATOP
|
||||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
help
|
||||
This enables support for Freescale i.MX7 Dual processor.
|
||||
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
|
|||
unsigned pad = pin & IOMUX_PADNUM_MASK;
|
||||
|
||||
if (pad >= (PIN_MAX + 1)) {
|
||||
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
|
||||
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n",
|
||||
pad, label ? label : "?");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ static void __init imx6ul_init_late(void)
|
|||
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static const char *imx6ul_dt_compat[] __initconst = {
|
||||
static const char * const imx6ul_dt_compat[] __initconst = {
|
||||
"fsl,imx6ul",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -105,6 +105,11 @@ static void __init imx7d_init_irq(void)
|
|||
irqchip_init();
|
||||
}
|
||||
|
||||
static void __init imx7d_init_late(void)
|
||||
{
|
||||
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static const char *const imx7d_dt_compat[] __initconst = {
|
||||
"fsl,imx7d",
|
||||
NULL,
|
||||
|
|
@ -112,6 +117,7 @@ static const char *const imx7d_dt_compat[] __initconst = {
|
|||
|
||||
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
|
||||
.init_irq = imx7d_init_irq,
|
||||
.init_late = imx7d_init_late,
|
||||
.init_machine = imx7d_init_machine,
|
||||
.dt_compat = imx7d_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -33,24 +33,6 @@
|
|||
#include "mmc.h"
|
||||
#include "sram.h"
|
||||
|
||||
#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
|
||||
|
||||
static struct platform_device omap_pcm = {
|
||||
.name = "omap-pcm-audio",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static void omap_init_audio(void)
|
||||
{
|
||||
platform_device_register(&omap_pcm);
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void omap_init_audio(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
|
||||
|
||||
#define OMAP_RTC_BASE 0xfffb4800
|
||||
|
|
@ -425,7 +407,6 @@ static int __init omap1_init_devices(void)
|
|||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
|
||||
omap_init_audio();
|
||||
omap_init_mbox();
|
||||
omap_init_rtc();
|
||||
omap_init_spi100k();
|
||||
|
|
|
|||
|
|
@ -223,8 +223,6 @@ obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
|
|||
# EMU peripherals
|
||||
obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
|
||||
|
||||
obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
|
||||
|
||||
# OMAP2420 MSDI controller integration support ("MMC")
|
||||
obj-$(CONFIG_SOC_OMAP2420) += msdi.o
|
||||
|
||||
|
|
|
|||
|
|
@ -1257,7 +1257,7 @@ static struct platform_device omap3_rom_rng_device = {
|
|||
static void __init rx51_init_omap3_rom_rng(void)
|
||||
{
|
||||
if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
|
||||
pr_info("RX-51: Registring OMAP3 HWRNG device\n");
|
||||
pr_info("RX-51: Registering OMAP3 HWRNG device\n");
|
||||
platform_device_register(&omap3_rom_rng_device);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -83,6 +83,14 @@ static struct clockdomain mmu_cfg_81xx_clkdm = {
|
|||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain default_l3_slow_81xx_clkdm = {
|
||||
.name = "default_l3_slow_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI81XX_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
/* 816x only */
|
||||
|
||||
static struct clockdomain alwon_mpu_816x_clkdm = {
|
||||
|
|
@ -96,7 +104,7 @@ static struct clockdomain alwon_mpu_816x_clkdm = {
|
|||
static struct clockdomain active_gem_816x_clkdm = {
|
||||
.name = "active_gem_clkdm",
|
||||
.pwrdm = { .name = "active_pwrdm" },
|
||||
.cm_inst = TI816X_CM_ACTIVE_MOD,
|
||||
.cm_inst = TI81XX_CM_ACTIVE_MOD,
|
||||
.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
|
@ -128,7 +136,7 @@ static struct clockdomain ivahd2_816x_clkdm = {
|
|||
static struct clockdomain sgx_816x_clkdm = {
|
||||
.name = "sgx_clkdm",
|
||||
.pwrdm = { .name = "sgx_pwrdm" },
|
||||
.cm_inst = TI816X_CM_SGX_MOD,
|
||||
.cm_inst = TI81XX_CM_SGX_MOD,
|
||||
.clkdm_offs = TI816X_CM_SGX_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
|
@ -136,7 +144,7 @@ static struct clockdomain sgx_816x_clkdm = {
|
|||
static struct clockdomain default_l3_med_816x_clkdm = {
|
||||
.name = "default_l3_med_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.cm_inst = TI81XX_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
|
@ -144,7 +152,7 @@ static struct clockdomain default_l3_med_816x_clkdm = {
|
|||
static struct clockdomain default_ducati_816x_clkdm = {
|
||||
.name = "default_ducati_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.cm_inst = TI81XX_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
|
@ -152,19 +160,11 @@ static struct clockdomain default_ducati_816x_clkdm = {
|
|||
static struct clockdomain default_pci_816x_clkdm = {
|
||||
.name = "default_pci_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.cm_inst = TI81XX_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain default_l3_slow_816x_clkdm = {
|
||||
.name = "default_l3_slow_clkdm",
|
||||
.pwrdm = { .name = "default_pwrdm" },
|
||||
.cm_inst = TI816X_CM_DEFAULT_MOD,
|
||||
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
|
||||
.flags = CLKDM_CAN_SWSUP,
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_ti814x[] __initdata = {
|
||||
&alwon_l3_slow_81xx_clkdm,
|
||||
&alwon_l3_med_81xx_clkdm,
|
||||
|
|
@ -172,6 +172,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
|
|||
&alwon_ethernet_81xx_clkdm,
|
||||
&mmu_81xx_clkdm,
|
||||
&mmu_cfg_81xx_clkdm,
|
||||
&default_l3_slow_81xx_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -198,7 +199,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
|
|||
&default_l3_med_816x_clkdm,
|
||||
&default_ducati_816x_clkdm,
|
||||
&default_pci_816x_clkdm,
|
||||
&default_l3_slow_816x_clkdm,
|
||||
&default_l3_slow_81xx_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,15 +18,15 @@
|
|||
#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
|
||||
|
||||
/* TI81XX common CM module offsets */
|
||||
#define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
|
||||
#define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
|
||||
#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
|
||||
#define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
|
||||
|
||||
/* TI816X CM module offsets */
|
||||
#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */
|
||||
#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */
|
||||
#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
|
||||
#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
|
||||
#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
|
||||
#define TI816X_CM_SGX_MOD 0x0900 /* 256B */
|
||||
|
||||
/* ALWON */
|
||||
#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
|
||||
|
|
|
|||
|
|
@ -94,22 +94,6 @@ static inline void omap_init_mbox(void) { }
|
|||
|
||||
static inline void omap_init_sti(void) {}
|
||||
|
||||
#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
|
||||
|
||||
static struct platform_device omap_pcm = {
|
||||
.name = "omap-pcm-audio",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static void omap_init_audio(void)
|
||||
{
|
||||
platform_device_register(&omap_pcm);
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void omap_init_audio(void) {}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
|
||||
|
||||
#include <linux/platform_data/spi-omap2-mcspi.h>
|
||||
|
|
@ -239,13 +223,12 @@ static int __init omap2_init_devices(void)
|
|||
if (!of_have_populated_dt())
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
/*
|
||||
* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
omap_init_audio();
|
||||
/* If dtb is there, the devices will be created dynamically */
|
||||
if (!of_have_populated_dt()) {
|
||||
/*
|
||||
* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
omap_init_mbox();
|
||||
omap_init_mcspi();
|
||||
omap_init_sham();
|
||||
|
|
|
|||
|
|
@ -488,6 +488,7 @@ void __init omap3xxx_check_revision(void)
|
|||
}
|
||||
break;
|
||||
case 0xb8f2:
|
||||
case 0xb968:
|
||||
switch (rev) {
|
||||
case 0:
|
||||
/* FALLTHROUGH */
|
||||
|
|
@ -511,7 +512,8 @@ void __init omap3xxx_check_revision(void)
|
|||
/* Unknown default to latest silicon rev as default */
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
cpu_rev = "1.2";
|
||||
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
|
||||
pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
|
||||
hawkeye);
|
||||
}
|
||||
sprintf(soc_rev, "ES%s", cpu_rev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
/*
|
||||
* omap iommu: omap device registration
|
||||
*
|
||||
* Copyright (C) 2008-2009 Nokia Corporation
|
||||
*
|
||||
* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/platform_data/iommu-omap.h>
|
||||
#include "soc.h"
|
||||
#include "omap_hwmod.h"
|
||||
#include "omap_device.h"
|
||||
|
||||
static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct iommu_platform_data *pdata;
|
||||
struct omap_mmu_dev_attr *a = (struct omap_mmu_dev_attr *)oh->dev_attr;
|
||||
static int i;
|
||||
|
||||
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
pdata->name = oh->name;
|
||||
pdata->nr_tlb_entries = a->nr_tlb_entries;
|
||||
|
||||
if (oh->rst_lines_cnt == 1) {
|
||||
pdata->reset_name = oh->rst_lines->name;
|
||||
pdata->assert_reset = omap_device_assert_hardreset;
|
||||
pdata->deassert_reset = omap_device_deassert_hardreset;
|
||||
}
|
||||
|
||||
pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata));
|
||||
|
||||
kfree(pdata);
|
||||
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("%s: device build err: %ld\n", __func__, PTR_ERR(pdev));
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
|
||||
i++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init omap_iommu_init(void)
|
||||
{
|
||||
/* If dtb is there, the devices will be created dynamically */
|
||||
if (of_have_populated_dt())
|
||||
return -ENODEV;
|
||||
|
||||
return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
|
||||
}
|
||||
omap_subsys_initcall(omap_iommu_init);
|
||||
/* must be ready before omap3isp is probed */
|
||||
|
|
@ -62,4 +62,4 @@ static int __init omap2xxx_common_look_up_clks_for_reset(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
omap_core_initcall(omap2xxx_common_look_up_clks_for_reset);
|
||||
omap_postcore_initcall(omap2xxx_common_look_up_clks_for_reset);
|
||||
|
|
|
|||
|
|
@ -869,7 +869,7 @@ static int __init omap_device_init(void)
|
|||
bus_register_notifier(&platform_bus_type, &platform_nb);
|
||||
return 0;
|
||||
}
|
||||
omap_core_initcall(omap_device_init);
|
||||
omap_postcore_initcall(omap_device_init);
|
||||
|
||||
/**
|
||||
* omap_device_late_idle - idle devices without drivers
|
||||
|
|
|
|||
|
|
@ -3313,7 +3313,7 @@ static int __init omap_hwmod_setup_all(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
omap_core_initcall(omap_hwmod_setup_all);
|
||||
omap_postcore_initcall(omap_hwmod_setup_all);
|
||||
|
||||
/**
|
||||
* omap_hwmod_enable - enable an omap_hwmod
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
#include "l4_3xxx.h"
|
||||
#include <linux/platform_data/asoc-ti-mcbsp.h>
|
||||
#include <linux/platform_data/spi-omap2-mcspi.h>
|
||||
#include <linux/platform_data/iommu-omap.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
|
@ -2957,80 +2956,40 @@ static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
|
|||
};
|
||||
|
||||
/* mmu isp */
|
||||
|
||||
static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
|
||||
.nr_tlb_entries = 8,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
|
||||
{ .irq = 24 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x480bd400,
|
||||
.pa_end = 0x480bd47f,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mmu isp */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_mmu_isp_hwmod,
|
||||
.addr = omap3xxx_mmu_isp_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
|
||||
.name = "mmu_isp",
|
||||
.class = &omap3xxx_mmu_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mmu_isp_irqs,
|
||||
.main_clk = "cam_ick",
|
||||
.dev_attr = &mmu_isp_dev_attr,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* mmu iva */
|
||||
|
||||
static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
|
||||
.nr_tlb_entries = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
|
||||
{ .irq = 28 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
|
||||
{ .name = "mmu", .rst_shift = 1, .st_shift = 9 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x5d000000,
|
||||
.pa_end = 0x5d00007f,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main -> iva mmu */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
|
||||
.master = &omap3xxx_l3_main_hwmod,
|
||||
.slave = &omap3xxx_mmu_iva_hwmod,
|
||||
.addr = omap3xxx_mmu_iva_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
|
||||
.name = "mmu_iva",
|
||||
.class = &omap3xxx_mmu_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_mmu_iva_irqs,
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.rst_lines = omap3xxx_mmu_iva_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
|
||||
|
|
@ -3043,7 +3002,6 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
|
|||
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmu_iva_dev_attr,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
|
||||
#include <linux/platform_data/spi-omap2-mcspi.h>
|
||||
#include <linux/platform_data/asoc-ti-mcbsp.h>
|
||||
#include <linux/platform_data/iommu-omap.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "omap_hwmod.h"
|
||||
|
|
@ -2088,30 +2087,16 @@ static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
|
|||
|
||||
/* mmu ipu */
|
||||
|
||||
static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
|
||||
.nr_tlb_entries = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
|
||||
static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
|
||||
{ .name = "mmu_cache", .rst_shift = 2 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x55082000,
|
||||
.pa_end = 0x550820ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l3_main_2 -> mmu_ipu */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_mmu_ipu_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.addr = omap44xx_mmu_ipu_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -2130,35 +2115,20 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
|
|||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmu_ipu_dev_attr,
|
||||
};
|
||||
|
||||
/* mmu dsp */
|
||||
|
||||
static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
|
||||
.nr_tlb_entries = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
|
||||
static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
|
||||
{ .name = "mmu_cache", .rst_shift = 1 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a066000,
|
||||
.pa_end = 0x4a0660ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_cfg -> dsp */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_mmu_dsp_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_mmu_dsp_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
@ -2177,7 +2147,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
|
|||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmu_dsp_dev_attr,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -3915,21 +3884,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48078000,
|
||||
.pa_end = 0x48078fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_per -> elm */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
|
||||
.master = &omap44xx_l4_per_hwmod,
|
||||
.slave = &omap44xx_elm_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_elm_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2103,7 +2103,7 @@ static struct omap_hwmod dra7xx_uart4_hwmod = {
|
|||
.class = &dra7xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.main_clk = "uart4_gfclk_mux",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
|
||||
|
|
|
|||
|
|
@ -104,8 +104,8 @@
|
|||
* The default .clkctrl_offs field is offset from CM_DEFAULT, that's
|
||||
* TRM 18.7.6 CM_DEFAULT device register values minus 0x500
|
||||
*/
|
||||
#define DM816X_CM_DEFAULT_OFFSET 0x500
|
||||
#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
|
||||
#define DM81XX_CM_DEFAULT_OFFSET 0x500
|
||||
#define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
|
||||
|
||||
/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
|
||||
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
|
||||
|
|
@ -557,22 +557,42 @@ static struct omap_hwmod_class dm81xx_usbotg_class = {
|
|||
.sysc = &dm81xx_usbhsotg_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_usbss_hwmod = {
|
||||
static struct omap_hwmod dm814x_usbss_hwmod = {
|
||||
.name = "usb_otg_hs",
|
||||
.clkdm_name = "default_l3_slow_clkdm",
|
||||
.main_clk = "sysclk6_ck",
|
||||
.main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL,
|
||||
.clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.class = &dm81xx_usbotg_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
|
||||
static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
|
||||
.master = &dm81xx_default_l3_slow_hwmod,
|
||||
.slave = &dm81xx_usbss_hwmod,
|
||||
.slave = &dm814x_usbss_hwmod,
|
||||
.clk = "sysclk6_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm816x_usbss_hwmod = {
|
||||
.name = "usb_otg_hs",
|
||||
.clkdm_name = "default_l3_slow_clkdm",
|
||||
.main_clk = "sysclk6_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.class = &dm81xx_usbotg_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
|
||||
.master = &dm81xx_default_l3_slow_hwmod,
|
||||
.slave = &dm816x_usbss_hwmod,
|
||||
.clk = "sysclk6_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
|
@ -912,7 +932,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
|
||||
static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
|
||||
.rev_offs = 0x0,
|
||||
.sysc_offs = 0x110,
|
||||
.syss_offs = 0x114,
|
||||
|
|
@ -923,24 +943,94 @@ static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
|
|||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm816x_mmc_class = {
|
||||
static struct omap_hwmod_class dm81xx_mmc_class = {
|
||||
.name = "mmc",
|
||||
.sysc = &dm816x_mmc_sysc,
|
||||
.sysc = &dm81xx_mmc_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = {
|
||||
static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
|
||||
{ .role = "dbck", .clk = "sysclk18_ck", },
|
||||
};
|
||||
|
||||
static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
|
||||
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
||||
static struct omap_hsmmc_dev_attr mmc_dev_attr = {
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm814x_mmc1_hwmod = {
|
||||
.name = "mmc1",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.opt_clks = dm81xx_mmc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
|
||||
.main_clk = "sysclk8_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmc_dev_attr,
|
||||
.class = &dm81xx_mmc_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
|
||||
.master = &dm81xx_l4_ls_hwmod,
|
||||
.slave = &dm814x_mmc1_hwmod,
|
||||
.clk = "sysclk6_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
.flags = OMAP_FIREWALL_L4
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm814x_mmc2_hwmod = {
|
||||
.name = "mmc2",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.opt_clks = dm81xx_mmc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
|
||||
.main_clk = "sysclk8_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmc_dev_attr,
|
||||
.class = &dm81xx_mmc_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
|
||||
.master = &dm81xx_l4_ls_hwmod,
|
||||
.slave = &dm814x_mmc2_hwmod,
|
||||
.clk = "sysclk6_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
.flags = OMAP_FIREWALL_L4
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm814x_mmc3_hwmod = {
|
||||
.name = "mmc3",
|
||||
.clkdm_name = "alwon_l3_med_clkdm",
|
||||
.opt_clks = dm81xx_mmc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
|
||||
.main_clk = "sysclk8_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmc_dev_attr,
|
||||
.class = &dm81xx_mmc_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
|
||||
.master = &dm81xx_alwon_l3_med_hwmod,
|
||||
.slave = &dm814x_mmc3_hwmod,
|
||||
.clk = "sysclk4_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm816x_mmc1_hwmod = {
|
||||
.name = "mmc1",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.opt_clks = dm816x_mmc1_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks),
|
||||
.opt_clks = dm81xx_mmc_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
|
||||
.main_clk = "sysclk10_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
|
|
@ -948,8 +1038,8 @@ static struct omap_hwmod dm816x_mmc1_hwmod = {
|
|||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &mmc1_dev_attr,
|
||||
.class = &dm816x_mmc_class,
|
||||
.dev_attr = &mmc_dev_attr,
|
||||
.class = &dm81xx_mmc_class,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
|
||||
|
|
@ -1036,6 +1126,40 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
|
|||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
|
||||
.rev_offs = 0x000,
|
||||
.sysc_offs = 0x010,
|
||||
.syss_offs = 0x014,
|
||||
.sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
|
||||
.idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
|
||||
.name = "spinbox",
|
||||
.sysc = &dm81xx_spinbox_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod dm81xx_spinbox_hwmod = {
|
||||
.name = "spinbox",
|
||||
.clkdm_name = "alwon_l3s_clkdm",
|
||||
.class = &dm81xx_spinbox_hwmod_class,
|
||||
.main_clk = "sysclk6_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
|
||||
.master = &dm81xx_l4_ls_hwmod,
|
||||
.slave = &dm81xx_spinbox_hwmod,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
|
||||
.name = "tpcc",
|
||||
};
|
||||
|
|
@ -1231,8 +1355,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
|
|||
/*
|
||||
* REVISIT: Test and enable the following once clocks work:
|
||||
* dm81xx_l4_ls__mailbox
|
||||
* dm81xx_alwon_l3_slow__gpmc
|
||||
* dm81xx_default_l3_slow__usbss
|
||||
*
|
||||
* Also note that some devices share a single clkctrl_offs..
|
||||
* For example, i2c1 and 3 share one, and i2c2 and 4 share one.
|
||||
|
|
@ -1252,6 +1374,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
|
|||
&dm81xx_l4_ls__gpio2,
|
||||
&dm81xx_l4_ls__elm,
|
||||
&dm81xx_l4_ls__mcspi1,
|
||||
&dm814x_l4_ls__mmc1,
|
||||
&dm814x_l4_ls__mmc2,
|
||||
&dm81xx_alwon_l3_fast__tpcc,
|
||||
&dm81xx_alwon_l3_fast__tptc0,
|
||||
&dm81xx_alwon_l3_fast__tptc1,
|
||||
|
|
@ -1265,6 +1389,9 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
|
|||
&dm814x_l4_ls__timer2,
|
||||
&dm814x_l4_hs__cpgmac0,
|
||||
&dm814x_cpgmac0__mdio,
|
||||
&dm81xx_alwon_l3_slow__gpmc,
|
||||
&dm814x_default_l3_slow__usbss,
|
||||
&dm814x_alwon_l3_med__mmc3,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -1298,6 +1425,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
|
|||
&dm816x_l4_ls__timer7,
|
||||
&dm81xx_l4_ls__mcspi1,
|
||||
&dm81xx_l4_ls__mailbox,
|
||||
&dm81xx_l4_ls__spinbox,
|
||||
&dm81xx_l4_hs__emac0,
|
||||
&dm81xx_emac0__mdio,
|
||||
&dm816x_l4_hs__emac1,
|
||||
|
|
@ -1311,7 +1439,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
|
|||
&dm81xx_tptc2__alwon_l3_fast,
|
||||
&dm81xx_tptc3__alwon_l3_fast,
|
||||
&dm81xx_alwon_l3_slow__gpmc,
|
||||
&dm81xx_default_l3_slow__usbss,
|
||||
&dm816x_default_l3_slow__usbss,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ static void __init nokia_n900_legacy_init(void)
|
|||
pr_warn("Thumb binaries may crash randomly without this workaround\n");
|
||||
}
|
||||
|
||||
pr_info("RX-51: Registring OMAP3 HWRNG device\n");
|
||||
pr_info("RX-51: Registering OMAP3 HWRNG device\n");
|
||||
platform_device_register(&omap3_rom_rng_device);
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -384,14 +384,14 @@ static struct powerdomain isp_814x_pwrdm = {
|
|||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain active_816x_pwrdm = {
|
||||
static struct powerdomain active_81xx_pwrdm = {
|
||||
.name = "active_pwrdm",
|
||||
.prcm_offs = TI816X_PRM_ACTIVE_MOD,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain default_816x_pwrdm = {
|
||||
static struct powerdomain default_81xx_pwrdm = {
|
||||
.name = "default_pwrdm",
|
||||
.prcm_offs = TI81XX_PRM_DEFAULT_MOD,
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
|
|
@ -486,6 +486,8 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
|
|||
static struct powerdomain *powerdomains_ti814x[] __initdata = {
|
||||
&alwon_81xx_pwrdm,
|
||||
&device_81xx_pwrdm,
|
||||
&active_81xx_pwrdm,
|
||||
&default_81xx_pwrdm,
|
||||
&gem_814x_pwrdm,
|
||||
&ivahd_814x_pwrdm,
|
||||
&hdvpss_814x_pwrdm,
|
||||
|
|
@ -497,8 +499,8 @@ static struct powerdomain *powerdomains_ti814x[] __initdata = {
|
|||
static struct powerdomain *powerdomains_ti816x[] __initdata = {
|
||||
&alwon_81xx_pwrdm,
|
||||
&device_81xx_pwrdm,
|
||||
&active_816x_pwrdm,
|
||||
&default_816x_pwrdm,
|
||||
&active_81xx_pwrdm,
|
||||
&default_81xx_pwrdm,
|
||||
&ivahd0_816x_pwrdm,
|
||||
&ivahd1_816x_pwrdm,
|
||||
&ivahd2_816x_pwrdm,
|
||||
|
|
|
|||
|
|
@ -213,7 +213,7 @@ static int __init omap_serial_early_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
omap_core_initcall(omap_serial_early_init);
|
||||
omap_postcore_initcall(omap_serial_early_init);
|
||||
|
||||
/**
|
||||
* omap_serial_init_port() - initialize single serial port
|
||||
|
|
|
|||
|
|
@ -194,8 +194,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
|
|||
/**
|
||||
* omap_dmtimer_init - initialisation function when device tree is used
|
||||
*
|
||||
* For secure OMAP3 devices, timers with device type "timer-secure" cannot
|
||||
* be used by the kernel as they are reserved. Therefore, to prevent the
|
||||
* For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
|
||||
* cannot be used by the kernel as they are reserved. Therefore, to prevent the
|
||||
* kernel registering these devices remove them dynamically from the device
|
||||
* tree on boot.
|
||||
*/
|
||||
|
|
@ -203,7 +203,7 @@ static void __init omap_dmtimer_init(void)
|
|||
{
|
||||
struct device_node *np;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
if (!cpu_is_omap34xx() && !soc_is_dra7xx())
|
||||
return;
|
||||
|
||||
/* If we are a secure device, remove any secure timer nodes */
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ static int ncores;
|
|||
#define PMU_PWRDN_SCU 4
|
||||
|
||||
static struct regmap *pmu;
|
||||
static int has_pmu = true;
|
||||
|
||||
static int pmu_power_domain_is_on(int pd)
|
||||
{
|
||||
|
|
@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
|
|||
if (!IS_ERR(rstc) && !on)
|
||||
reset_control_assert(rstc);
|
||||
|
||||
ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: could not update power domain\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = -1;
|
||||
while (ret != on) {
|
||||
ret = pmu_power_domain_is_on(pd);
|
||||
if (has_pmu) {
|
||||
ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: could not read power domain state\n",
|
||||
pr_err("%s: could not update power domain\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = -1;
|
||||
while (ret != on) {
|
||||
ret = pmu_power_domain_is_on(pd);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: could not read power domain state\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!IS_ERR(rstc)) {
|
||||
|
|
@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (!sram_base_addr || !pmu) {
|
||||
if (!sram_base_addr || (has_pmu && !pmu)) {
|
||||
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
|
@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
return;
|
||||
}
|
||||
|
||||
if (rockchip_smp_prepare_pmu())
|
||||
if (has_pmu && rockchip_smp_prepare_pmu())
|
||||
return;
|
||||
|
||||
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
|
||||
|
|
@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
pmu_set_power_domain(0 + i, false);
|
||||
}
|
||||
|
||||
static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
has_pmu = false;
|
||||
|
||||
rockchip_smp_prepare_cpus(max_cpus);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static int rockchip_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
|
|
@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
|
|||
}
|
||||
#endif
|
||||
|
||||
static const struct smp_operations rk3036_smp_ops __initconst = {
|
||||
.smp_prepare_cpus = rk3036_smp_prepare_cpus,
|
||||
.smp_boot_secondary = rockchip_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = rockchip_cpu_kill,
|
||||
.cpu_die = rockchip_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct smp_operations rockchip_smp_ops __initconst = {
|
||||
.smp_prepare_cpus = rockchip_smp_prepare_cpus,
|
||||
.smp_boot_secondary = rockchip_boot_secondary,
|
||||
|
|
@ -349,4 +369,5 @@ static const struct smp_operations rockchip_smp_ops __initconst = {
|
|||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
|
||||
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ static const char * const rockchip_board_dt_compat[] = {
|
|||
"rockchip,rk3066a",
|
||||
"rockchip,rk3066b",
|
||||
"rockchip,rk3188",
|
||||
"rockchip,rk3228",
|
||||
"rockchip,rk3288",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
config ARCH_TANGO
|
||||
bool "Sigma Designs Tango4 (SMP87xx)" if ARCH_MULTI_V7
|
||||
# Cortex-A9 MPCore r3p0, PL310 r3p2
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369 if SMP
|
||||
select ARM_ERRATA_775420
|
||||
select ARM_GIC
|
||||
select CLKSRC_TANGO_XTAL
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_ARM_TWD
|
||||
select TANGO_IRQ
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o := -Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-y += setup.o smc.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include "smc.h"
|
||||
|
||||
static int tango_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
|
||||
tango_start_aux_core(cpu);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct smp_operations tango_smp_ops __initdata = {
|
||||
.smp_boot_secondary = tango_boot_secondary,
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango_smp_ops);
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "smc.h"
|
||||
|
||||
static void tango_l2c_write(unsigned long val, unsigned int reg)
|
||||
{
|
||||
if (reg == L2X0_CTRL)
|
||||
tango_set_l2_control(val);
|
||||
}
|
||||
|
||||
static const char *const tango_dt_compat[] = { "sigma,tango4", NULL };
|
||||
|
||||
DT_MACHINE_START(TANGO_DT, "Sigma Tango DT")
|
||||
.dt_compat = tango_dt_compat,
|
||||
.l2c_aux_mask = ~0,
|
||||
.l2c_write_sec = tango_l2c_write,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include <linux/linkage.h>
|
||||
|
||||
ENTRY(tango_smc)
|
||||
push {lr}
|
||||
mov ip, r1
|
||||
dsb /* This barrier is probably unnecessary */
|
||||
smc #0
|
||||
pop {pc}
|
||||
ENDPROC(tango_smc)
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
extern int tango_smc(unsigned int val, unsigned int service);
|
||||
|
||||
#define tango_set_l2_control(val) tango_smc(val, 0x102)
|
||||
#define tango_start_aux_core(val) tango_smc(val, 0x104)
|
||||
#define tango_set_aux_boot_addr(val) tango_smc((unsigned int)val, 0x105)
|
||||
|
|
@ -6,6 +6,7 @@ config ARCH_UNIPHIER
|
|||
select ARM_GIC
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select PINCTRL
|
||||
help
|
||||
Support for UniPhier SoC family developed by Socionext Inc.
|
||||
(formerly, System LSI Business Division of Panasonic Corporation)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
config ARCH_ZYNQ
|
||||
bool "Xilinx Zynq ARM Cortex A9 Platform"
|
||||
depends on ARCH_MULTI_V7
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/device.h>
|
||||
|
|
@ -137,6 +138,31 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
|
||||
{
|
||||
int ret;
|
||||
struct clk *parent;
|
||||
|
||||
/*
|
||||
* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
|
||||
* do not call clk_get() for these devices.
|
||||
*/
|
||||
if (!timer->fclk)
|
||||
return -ENODEV;
|
||||
|
||||
parent = clk_get(&timer->pdev->dev, NULL);
|
||||
if (IS_ERR(parent))
|
||||
return -ENODEV;
|
||||
|
||||
ret = clk_set_parent(timer->fclk, parent);
|
||||
if (ret < 0)
|
||||
pr_err("%s: failed to set parent\n", __func__);
|
||||
|
||||
clk_put(parent);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
|
||||
{
|
||||
int rc;
|
||||
|
|
@ -166,7 +192,11 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
|
|||
__omap_dm_timer_enable_posted(timer);
|
||||
omap_dm_timer_disable(timer);
|
||||
|
||||
return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
|
||||
rc = omap_dm_timer_of_set_source(timer);
|
||||
if (rc == -ENODEV)
|
||||
return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static inline u32 omap_dm_timer_reserved_systimer(int id)
|
||||
|
|
@ -504,6 +534,12 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
|||
if (IS_ERR(timer->fclk))
|
||||
return -EINVAL;
|
||||
|
||||
#if defined(CONFIG_COMMON_CLK)
|
||||
/* Check if the clock has configurable parents */
|
||||
if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
switch (source) {
|
||||
case OMAP_TIMER_SRC_SYS_CLK:
|
||||
parent_name = "timer_sys_ck";
|
||||
|
|
@ -943,6 +979,10 @@ static const struct of_device_id omap_timer_match[] = {
|
|||
.compatible = "ti,am335x-timer-1ms",
|
||||
.data = &omap3plus_pdata,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,dm816-timer",
|
||||
.data = &omap3plus_pdata,
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, omap_timer_match);
|
||||
|
|
|
|||
|
|
@ -29,15 +29,6 @@ struct omap_iommu_arch_data {
|
|||
struct omap_iommu *iommu_dev;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
|
||||
* @nr_tlb_entries: number of entries supported by the translation
|
||||
* look-aside buffer (TLB).
|
||||
*/
|
||||
struct omap_mmu_dev_attr {
|
||||
int nr_tlb_entries;
|
||||
};
|
||||
|
||||
struct iommu_platform_data {
|
||||
const char *name;
|
||||
const char *reset_name;
|
||||
|
|
|
|||
Loading…
Reference in New Issue