spi: initial BF54x SPI support
Initial BF54x SPI support - support BF54x SPI0 - clean up some code (whitespace etc) - will support multiports in the future - start using portmux calls Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>hifive-unleashed-5.1
Bryan Wu
Linus Torvalds
parent
c24b2602af
commit
131b17d42d
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@ -1,17 +1,20 @@
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/*
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* File: drivers/spi/bfin5xx_spi.c
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* Based on: N/A
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* Author: Luke Yang (Analog Devices Inc.)
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* File: drivers/spi/bfin5xx_spi.c
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* Maintainer:
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* Bryan Wu <bryan.wu@analog.com>
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* Original Author:
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* Luke Yang (Analog Devices Inc.)
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*
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* Created: March. 10th 2006
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* Description: SPI controller driver for Blackfin 5xx
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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* Created: March. 10th 2006
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* Description: SPI controller driver for Blackfin BF5xx
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Modified:
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* March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
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* August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
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* July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
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*
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* Copyright 2004-2006 Analog Devices Inc.
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* This program is free software ; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -31,27 +34,27 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/delay.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#include <asm/bfin5xx_spi.h>
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MODULE_AUTHOR("Luke Yang");
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MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");
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MODULE_AUTHOR("Bryan Wu, Luke Yang");
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MODULE_DESCRIPTION("Blackfin BF5xx SPI Contoller Driver");
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MODULE_LICENSE("GPL");
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#define DRV_NAME "bfin-spi-master"
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#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
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#define DEFINE_SPI_REG(reg, off) \
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@ -124,6 +127,7 @@ struct chip_data {
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u16 flag;
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u8 chip_select_num;
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u8 chip_select_requested;
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u8 n_bytes;
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u8 width; /* 0 or 1 */
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u8 enable_dma;
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@ -188,53 +192,37 @@ static void restore_state(struct driver_data *drv_data)
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bfin_spi_disable(drv_data);
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dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
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#if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
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dev_dbg(&drv_data->pdev->dev,
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if (!chip->chip_select_requested) {
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dev_dbg(&drv_data->pdev->dev,
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"chip select number is %d\n", chip->chip_select_num);
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switch (chip->chip_select_num) {
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case 1:
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
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SSYNC();
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break;
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case 2:
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case 3:
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
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SSYNC();
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
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SSYNC();
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break;
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switch (chip->chip_select_num) {
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case 1:
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peripheral_request(P_SPI0_SSEL1, DRV_NAME);
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break;
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case 2:
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peripheral_request(P_SPI0_SSEL2, DRV_NAME);
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break;
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case 3:
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peripheral_request(P_SPI0_SSEL3, DRV_NAME);
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break;
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case 4:
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peripheral_request(P_SPI0_SSEL4, DRV_NAME);
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break;
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case 5:
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peripheral_request(P_SPI0_SSEL5, DRV_NAME);
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break;
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case 6:
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peripheral_request(P_SPI0_SSEL6, DRV_NAME);
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break;
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case 7:
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peripheral_request(P_SPI0_SSEL7, DRV_NAME);
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break;
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}
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case 4:
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
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SSYNC();
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
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SSYNC();
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break;
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case 5:
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
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SSYNC();
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
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SSYNC();
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break;
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case 6:
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
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SSYNC();
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
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SSYNC();
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break;
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case 7:
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bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
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SSYNC();
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bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
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SSYNC();
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break;
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chip->chip_select_requested = 1;
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}
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#endif
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/* Load the registers */
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write_CTRL(chip->ctl_reg);
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@ -277,7 +265,7 @@ static void null_reader(struct driver_data *drv_data)
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static void u8_writer(struct driver_data *drv_data)
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{
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"cr8-s is 0x%x\n", read_STAT());
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(*(u8 *) (drv_data->tx));
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@ -316,7 +304,7 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
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static void u8_reader(struct driver_data *drv_data)
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{
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"cr-8 is 0x%x\n", read_STAT());
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/* clear TDBR buffer before read(else it will be shifted out) */
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@ -403,7 +391,7 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
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static void u16_writer(struct driver_data *drv_data)
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{
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"cr16 is 0x%x\n", read_STAT());
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while (drv_data->tx < drv_data->tx_end) {
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@ -700,9 +688,9 @@ static void pump_transfers(unsigned long data)
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drv_data->write = drv_data->tx ? chip->write : null_writer;
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drv_data->read = drv_data->rx ? chip->read : null_reader;
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drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
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dev_dbg(&drv_data->pdev->dev,
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"transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
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drv_data->write, chip->write, null_writer);
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dev_dbg(&drv_data->pdev->dev, "transfer: ",
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"drv_data->write is %p, chip->write is %p, null_wr is %p\n",
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drv_data->write, chip->write, null_writer);
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/* speed and width has been set on per message */
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message->state = RUNNING_STATE;
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@ -816,7 +804,7 @@ static void pump_transfers(unsigned long data)
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/* full duplex mode */
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BUG_ON((drv_data->tx_end - drv_data->tx) !=
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(drv_data->rx_end - drv_data->rx));
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cr = (read_CTRL() & (~BIT_CTL_TIMOD));
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cr = (read_CTRL() & (~BIT_CTL_TIMOD));
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cr |= CFG_SPI_WRITE | (width << 8) |
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(CFG_SPI_ENABLE << 14);
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dev_dbg(&drv_data->pdev->dev,
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@ -834,7 +822,7 @@ static void pump_transfers(unsigned long data)
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cr = (read_CTRL() & (~BIT_CTL_TIMOD));
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cr |= CFG_SPI_WRITE | (width << 8) |
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(CFG_SPI_ENABLE << 14);
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"IO write: cr is 0x%x\n", cr);
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write_CTRL(cr);
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@ -849,7 +837,7 @@ static void pump_transfers(unsigned long data)
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cr = (read_CTRL() & (~BIT_CTL_TIMOD));
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cr |= CFG_SPI_READ | (width << 8) |
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(CFG_SPI_ENABLE << 14);
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"IO read: cr is 0x%x\n", cr);
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write_CTRL(cr);
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@ -861,7 +849,7 @@ static void pump_transfers(unsigned long data)
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}
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if (!tranf_success) {
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"IO write error!\n");
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message->state = ERROR_STATE;
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} else {
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@ -881,9 +869,11 @@ static void pump_transfers(unsigned long data)
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/* pop a msg from queue and kick off real transfer */
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static void pump_messages(struct work_struct *work)
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{
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struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages);
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struct driver_data *drv_data;
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unsigned long flags;
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drv_data = container_of(work, struct driver_data, pump_messages);
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/* Lock queue and check for queue work */
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spin_lock_irqsave(&drv_data->lock, flags);
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if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
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@ -916,8 +906,8 @@ static void pump_messages(struct work_struct *work)
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"got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
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drv_data->cur_chip->baud, drv_data->cur_chip->flag,
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drv_data->cur_chip->ctl_reg);
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dev_dbg(&drv_data->pdev->dev,
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dev_dbg(&drv_data->pdev->dev,
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"the first transfer len is %d\n",
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drv_data->cur_transfer->len);
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@ -1193,6 +1183,15 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
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dev_err(&pdev->dev, "can not alloc spi_master\n");
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return -ENOMEM;
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}
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if (peripheral_request(P_SPI0_SCK, DRV_NAME) ||
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peripheral_request(P_SPI0_MISO, DRV_NAME) ||
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peripheral_request(P_SPI0_MOSI, DRV_NAME)) {
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dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
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goto out_error_queue_alloc;
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}
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drv_data = spi_master_get_devdata(master);
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drv_data->master = master;
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drv_data->master_info = platform_info;
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@ -1644,8 +1644,25 @@
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#define RESTART 0x20 /* Work Unit Transitions */
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#define DI_SEL 0x40 /* Data Interrupt Timing Select */
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#define DI_EN 0x80 /* Data Interrupt Enable */
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#define NDSIZE 0xf00 /* Flex Descriptor Size */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define DMAFLOW 0xf000 /* Next Operation */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
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