MIPS: KVM: Clean up TLB management hazards
KVM's host TLB handling routines were using tlbw hazard barrier macros around tlb_read(). Now that hazard barrier macros exist for tlbr, update this case to use them. Also fix various other unnecessary hazard barriers in this code. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -195,7 +195,6 @@ int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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return 0;
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}
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@ -219,15 +218,11 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
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old_entryhi = read_c0_entryhi();
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vaddr = badvaddr & (PAGE_MASK << 1);
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write_c0_entryhi(vaddr | kvm_mips_get_kernel_asid(vcpu));
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mtc0_tlbw_hazard();
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write_c0_entrylo0(entrylo0);
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mtc0_tlbw_hazard();
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write_c0_entrylo1(entrylo1);
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mtc0_tlbw_hazard();
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write_c0_index(kvm_mips_get_commpage_asid(vcpu));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0 (R): 0x%08lx, entrylo1(R): 0x%08lx\n",
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@ -237,7 +232,6 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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return 0;
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@ -291,7 +285,6 @@ int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr)
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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@ -322,21 +315,16 @@ int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va)
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if (idx > 0) {
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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mtc0_tlbw_hazard();
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write_c0_entrylo0(0);
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mtc0_tlbw_hazard();
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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}
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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@ -364,11 +352,11 @@ void kvm_mips_flush_host_tlb(int skip_kseg0)
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/* Blast 'em all away. */
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for (entry = 0; entry < maxentry; entry++) {
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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if (skip_kseg0) {
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mtc0_tlbr_hazard();
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tlb_read();
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tlbw_use_hazard();
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tlb_read_hazard();
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entryhi = read_c0_entryhi();
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@ -379,22 +367,17 @@ void kvm_mips_flush_host_tlb(int skip_kseg0)
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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mtc0_tlbw_hazard();
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write_c0_entrylo0(0);
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mtc0_tlbw_hazard();
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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}
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tlbw_use_hazard();
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write_c0_entryhi(old_entryhi);
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write_c0_pagemask(old_pagemask);
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mtc0_tlbw_hazard();
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tlbw_use_hazard();
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local_irq_restore(flags);
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}
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@ -419,9 +402,9 @@ void kvm_local_flush_tlb_all(void)
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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entry++;
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}
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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mtc0_tlbw_hazard();
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