pinctrl: qcom: use scm_call to route GPIO irq to Apps
For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed. Signed-off-by: Ajay Kishore <akisho@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -22,6 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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#include <linux/qcom_scm.h>
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#include <linux/io.h>
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#include <linux/soc/qcom/irq.h>
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@ -60,6 +62,8 @@ struct msm_pinctrl {
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struct irq_chip irq_chip;
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int irq;
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bool intr_target_use_scm;
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raw_spinlock_t lock;
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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@ -68,6 +72,7 @@ struct msm_pinctrl {
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs[MAX_NR_TILES];
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u32 phys_base[MAX_NR_TILES];
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};
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#define MSM_ACCESSOR(name) \
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@ -882,11 +887,31 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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/* Route interrupts to application cpu */
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val = msm_readl_intr_target(pctrl, g);
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val &= ~(7 << g->intr_target_bit);
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val |= g->intr_target_kpss_val << g->intr_target_bit;
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msm_writel_intr_target(val, pctrl, g);
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/* Route interrupts to application cpu.
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* With intr_target_use_scm interrupts are routed to
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* application cpu using scm calls.
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*/
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if (pctrl->intr_target_use_scm) {
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u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
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int ret;
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qcom_scm_io_readl(addr, &val);
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val &= ~(7 << g->intr_target_bit);
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val |= g->intr_target_kpss_val << g->intr_target_bit;
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ret = qcom_scm_io_writel(addr, val);
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if (ret)
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dev_err(pctrl->dev,
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"Failed routing %lu interrupt to Apps proc",
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d->hwirq);
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}
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} else {
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val = msm_readl_intr_target(pctrl, g);
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val &= ~(7 << g->intr_target_bit);
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val |= g->intr_target_kpss_val << g->intr_target_bit;
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msm_writel_intr_target(val, pctrl, g);
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}
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@ -1241,6 +1266,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
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pctrl->dev = &pdev->dev;
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pctrl->soc = soc_data;
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pctrl->chip = msm_gpio_template;
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pctrl->intr_target_use_scm = of_device_is_compatible(
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pctrl->dev->of_node,
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"qcom,ipq8064-pinctrl");
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raw_spin_lock_init(&pctrl->lock);
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@ -1253,9 +1281,12 @@ int msm_pinctrl_probe(struct platform_device *pdev,
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return PTR_ERR(pctrl->regs[i]);
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}
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} else {
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pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pctrl->regs[0]))
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return PTR_ERR(pctrl->regs[0]);
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pctrl->phys_base[0] = res->start;
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}
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msm_pinctrl_setup_pm_reset(pctrl);
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