drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()
The PFI credit programming performed during cdclk change on vlv/chv requires access to a register in the disp2d power well. So far we've abused pipe-A power domain for this, but now we have the more appropriate "display core" domain so let's make use of it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190701161534.6671-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
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@ -545,10 +545,10 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
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/* There are cases where we can end up here with power domains
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* off and a CDCLK frequency other than the minimum, like when
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* issuing a modeset without actually changing any display after
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* a system suspend. So grab the PIPE-A domain, which covers
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* a system suspend. So grab the display core domain, which covers
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* the HW blocks needed for the following programming.
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*/
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
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vlv_iosf_sb_get(dev_priv,
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BIT(VLV_IOSF_SB_CCK) |
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@ -606,7 +606,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
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vlv_program_pfi_credits(dev_priv);
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intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
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intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
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}
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static void chv_set_cdclk(struct drm_i915_private *dev_priv,
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@ -631,10 +631,10 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
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/* There are cases where we can end up here with power domains
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* off and a CDCLK frequency other than the minimum, like when
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* issuing a modeset without actually changing any display after
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* a system suspend. So grab the PIPE-A domain, which covers
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* a system suspend. So grab the display core domain, which covers
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* the HW blocks needed for the following programming.
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*/
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
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wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
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vlv_punit_get(dev_priv);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
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@ -653,7 +653,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
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vlv_program_pfi_credits(dev_priv);
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intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
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intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
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}
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static int bdw_calc_cdclk(int min_cdclk)
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