Rockchip-pinctrl fixes from Doug Anderson and suspend-specific
functions from Chris Zhong -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJUVpbfAAoJEPOmecmc0R2Bl14H/Rwmpp+KUPcudzSMpnfcqSKt s8B/EVa7I/eURz+5ZFg6kbkTYsT0N/81vGG3MbLT6609iHsxkfClYHkX2JQNBqIn mDYKCpbKPWxS0OrAhYPqG5ywiKEYWZb95DRRoXX7TKh7SFC+5nb/MC9gYtd0kKx4 4fibILzOteN7Besvu+Ma8JkPJZR6/sebFkGj51Rpucff91qkiicy4nSEdCwSq2F5 8neEX95FQlmf1rSPcdt2GY4hEvPAJBe9R2EPIaPy77p0uy3POmgMJNyK7d2b2dxU mV/AP2Pc71OPIfmKYP9LlWPP3AWS1thA8kFEEUjDJvaSVX5qbJggmptVFWQ884o= =/WZL -----END PGP SIGNATURE----- Merge tag 'v3.19-rockchip-pinctrl1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into devel Rockchip-pinctrl fixes from Doug Anderson and suspend-specific functions from Chris Zhong
This commit is contained in:
Linus Walleij
commit
13d6a11af6
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@ -856,27 +856,22 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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* function called from the gpiolib interface).
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*/
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static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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int pin, bool input)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct rockchip_pin_bank *bank;
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struct gpio_chip *chip;
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int pin, ret;
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int ret;
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unsigned long flags;
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u32 data;
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chip = range->gc;
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bank = gc_to_pin_bank(chip);
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pin = offset - chip->base;
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dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
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offset, range->name, pin, input ? "input" : "output");
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ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
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if (ret < 0)
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return ret;
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spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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/* set bit to 1 for output, 0 for input */
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if (!input)
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@ -885,9 +880,28 @@ static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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data &= ~BIT(pin);
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct gpio_chip *chip;
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int pin;
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chip = range->gc;
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pin = offset - chip->base;
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dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
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offset, range->name, pin, input ? "input" : "output");
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return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
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input);
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}
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static const struct pinmux_ops rockchip_pmx_ops = {
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.get_functions_count = rockchip_pmx_get_funcs_count,
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.get_function_name = rockchip_pmx_get_func_name,
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@ -917,8 +931,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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return false;
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}
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static int rockchip_gpio_direction_output(struct gpio_chip *gc,
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unsigned offset, int value);
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
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/* set the pin config settings for a specified pin */
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@ -959,9 +972,10 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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return rc;
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break;
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case PIN_CONFIG_OUTPUT:
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rc = rockchip_gpio_direction_output(&bank->gpio_chip,
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pin - bank->pin_base,
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arg);
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rockchip_gpio_set(&bank->gpio_chip,
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pin - bank->pin_base, arg);
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rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
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pin - bank->pin_base, false);
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if (rc)
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return rc;
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break;
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@ -1253,6 +1267,10 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
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}
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}
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ret = rockchip_pinctrl_parse_dt(pdev, info);
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if (ret)
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return ret;
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info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
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if (!info->pctl_dev) {
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dev_err(&pdev->dev, "could not register pinctrl driver\n");
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@ -1270,12 +1288,6 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
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pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
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}
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ret = rockchip_pinctrl_parse_dt(pdev, info);
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if (ret) {
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pinctrl_unregister(info->pctl_dev);
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return ret;
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}
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return 0;
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}
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@ -1387,6 +1399,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
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u32 polarity = 0, data = 0;
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u32 pend;
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bool edge_changed = false;
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unsigned long flags;
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dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
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@ -1432,10 +1445,14 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
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if (bank->toggle_edge_mode && edge_changed) {
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/* Interrupt params should only be set with ints disabled */
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spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_INTEN);
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writel_relaxed(0, bank->reg_base + GPIO_INTEN);
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writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
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writel(data, bank->reg_base + GPIO_INTEN);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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chained_irq_exit(chip, desc);
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@ -1449,6 +1466,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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u32 polarity;
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u32 level;
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u32 data;
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unsigned long flags;
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int ret;
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/* make sure the pin is configured as gpio input */
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@ -1456,15 +1474,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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if (ret < 0)
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return ret;
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spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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data &= ~mask;
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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spin_unlock_irqrestore(&bank->slock, flags);
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if (type & IRQ_TYPE_EDGE_BOTH)
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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else
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__irq_set_handler_locked(d->irq, handle_level_irq);
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spin_lock_irqsave(&bank->slock, flags);
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irq_gc_lock(gc);
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level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
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@ -1507,6 +1530,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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break;
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default:
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irq_gc_unlock(gc);
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spin_unlock_irqrestore(&bank->slock, flags);
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return -EINVAL;
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}
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@ -1514,6 +1538,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
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irq_gc_unlock(gc);
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spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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@ -1563,6 +1588,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
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gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
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gc->wake_enabled = IRQ_MSK(bank->nr_pins);
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irq_set_handler_data(bank->irq, bank);
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irq_set_chained_handler(bank->irq, rockchip_irq_demux);
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@ -1770,6 +1796,51 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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return ctrl;
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}
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#define RK3288_GRF_GPIO6C_IOMUX 0x64
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#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
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static u32 rk3288_grf_gpio6c_iomux;
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static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
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{
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struct rockchip_pinctrl *info = dev_get_drvdata(dev);
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int ret = pinctrl_force_sleep(info->pctl_dev);
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if (ret)
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return ret;
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/*
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* RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
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* the setting here, and restore it at resume.
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*/
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if (info->ctrl->type == RK3288) {
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ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
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&rk3288_grf_gpio6c_iomux);
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if (ret) {
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pinctrl_force_default(info->pctl_dev);
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return ret;
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}
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}
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return 0;
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}
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static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
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{
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struct rockchip_pinctrl *info = dev_get_drvdata(dev);
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int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
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rk3288_grf_gpio6c_iomux |
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GPIO6C6_SEL_WRITE_ENABLE);
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if (ret)
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return ret;
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return pinctrl_force_default(info->pctl_dev);
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}
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static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
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rockchip_pinctrl_resume);
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static int rockchip_pinctrl_probe(struct platform_device *pdev)
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{
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struct rockchip_pinctrl *info;
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@ -1983,6 +2054,7 @@ static struct platform_driver rockchip_pinctrl_driver = {
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.driver = {
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.name = "rockchip-pinctrl",
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.owner = THIS_MODULE,
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.pm = &rockchip_pinctrl_dev_pm_ops,
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.of_match_table = rockchip_pinctrl_dt_match,
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},
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};
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