s2io.c: Shorten code line length by using intermediate pointers
Repeated variable use and line wrapping is hard to read. Use temp variables instead of direct references. struct fifo_info *fifo = &mac_control->fifos[i]; struct ring_info *ring = &mac_control->rings[i]; struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
6fce365df8
commit
13d866a9c9
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@ -364,13 +364,19 @@ static void s2io_vlan_rx_register(struct net_device *dev,
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struct mac_info *mac_control = &nic->mac_control;
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struct config_param *config = &nic->config;
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for (i = 0; i < config->tx_fifo_num; i++)
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spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
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for (i = 0; i < config->tx_fifo_num; i++) {
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struct fifo_info *fifo = &mac_control->fifos[i];
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spin_lock_irqsave(&fifo->tx_lock, flags[i]);
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}
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nic->vlgrp = grp;
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for (i = config->tx_fifo_num - 1; i >= 0; i--)
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spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
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flags[i]);
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for (i = config->tx_fifo_num - 1; i >= 0; i--) {
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struct fifo_info *fifo = &mac_control->fifos[i];
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spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
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}
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}
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/* Unregister the vlan */
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@ -382,15 +388,20 @@ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
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struct mac_info *mac_control = &nic->mac_control;
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struct config_param *config = &nic->config;
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for (i = 0; i < config->tx_fifo_num; i++)
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spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
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for (i = 0; i < config->tx_fifo_num; i++) {
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struct fifo_info *fifo = &mac_control->fifos[i];
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spin_lock_irqsave(&fifo->tx_lock, flags[i]);
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}
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if (nic->vlgrp)
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vlan_group_set_device(nic->vlgrp, vid, NULL);
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for (i = config->tx_fifo_num - 1; i >= 0; i--)
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spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
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flags[i]);
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for (i = config->tx_fifo_num - 1; i >= 0; i--) {
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struct fifo_info *fifo = &mac_control->fifos[i];
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spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
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}
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}
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/*
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@ -635,11 +646,12 @@ static int init_shared_mem(struct s2io_nic *nic)
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mac_control = &nic->mac_control;
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config = &nic->config;
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/* Allocation and initialization of TXDLs in FIOFs */
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/* Allocation and initialization of TXDLs in FIFOs */
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size = 0;
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for (i = 0; i < config->tx_fifo_num; i++) {
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size += config->tx_cfg[i].fifo_len;
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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size += tx_cfg->fifo_len;
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}
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if (size > MAX_AVAILABLE_TXDS) {
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DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
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@ -649,7 +661,9 @@ static int init_shared_mem(struct s2io_nic *nic)
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size = 0;
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for (i = 0; i < config->tx_fifo_num; i++) {
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size = config->tx_cfg[i].fifo_len;
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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size = tx_cfg->fifo_len;
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/*
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* Legal values are from 2 to 8192
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*/
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@ -666,11 +680,13 @@ static int init_shared_mem(struct s2io_nic *nic)
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lst_per_page = PAGE_SIZE / lst_size;
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for (i = 0; i < config->tx_fifo_num; i++) {
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int fifo_len = config->tx_cfg[i].fifo_len;
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struct fifo_info *fifo = &mac_control->fifos[i];
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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int fifo_len = tx_cfg->fifo_len;
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int list_holder_size = fifo_len * sizeof(struct list_info_hold);
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mac_control->fifos[i].list_info = kzalloc(list_holder_size,
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GFP_KERNEL);
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if (!mac_control->fifos[i].list_info) {
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fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
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if (!fifo->list_info) {
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DBG_PRINT(INFO_DBG,
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"Malloc failed for list_info\n");
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return -ENOMEM;
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@ -680,16 +696,17 @@ static int init_shared_mem(struct s2io_nic *nic)
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for (i = 0; i < config->tx_fifo_num; i++) {
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int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
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lst_per_page);
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mac_control->fifos[i].tx_curr_put_info.offset = 0;
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mac_control->fifos[i].tx_curr_put_info.fifo_len =
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config->tx_cfg[i].fifo_len - 1;
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mac_control->fifos[i].tx_curr_get_info.offset = 0;
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mac_control->fifos[i].tx_curr_get_info.fifo_len =
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config->tx_cfg[i].fifo_len - 1;
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mac_control->fifos[i].fifo_no = i;
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mac_control->fifos[i].nic = nic;
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mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
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mac_control->fifos[i].dev = dev;
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struct fifo_info *fifo = &mac_control->fifos[i];
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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fifo->tx_curr_put_info.offset = 0;
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fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
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fifo->tx_curr_get_info.offset = 0;
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fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
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fifo->fifo_no = i;
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fifo->nic = nic;
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fifo->max_txds = MAX_SKB_FRAGS + 2;
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fifo->dev = dev;
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for (j = 0; j < page_num; j++) {
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int k = 0;
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@ -726,11 +743,11 @@ static int init_shared_mem(struct s2io_nic *nic)
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}
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while (k < lst_per_page) {
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int l = (j * lst_per_page) + k;
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if (l == config->tx_cfg[i].fifo_len)
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if (l == tx_cfg->fifo_len)
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break;
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mac_control->fifos[i].list_info[l].list_virt_addr =
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fifo->list_info[l].list_virt_addr =
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tmp_v + (k * lst_size);
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mac_control->fifos[i].list_info[l].list_phy_addr =
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fifo->list_info[l].list_phy_addr =
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tmp_p + (k * lst_size);
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k++;
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}
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@ -738,10 +755,12 @@ static int init_shared_mem(struct s2io_nic *nic)
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}
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for (i = 0; i < config->tx_fifo_num; i++) {
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size = config->tx_cfg[i].fifo_len;
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mac_control->fifos[i].ufo_in_band_v
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= kcalloc(size, sizeof(u64), GFP_KERNEL);
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if (!mac_control->fifos[i].ufo_in_band_v)
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struct fifo_info *fifo = &mac_control->fifos[i];
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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size = tx_cfg->fifo_len;
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fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
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if (!fifo->ufo_in_band_v)
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return -ENOMEM;
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mem_allocated += (size * sizeof(u64));
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}
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@ -749,20 +768,19 @@ static int init_shared_mem(struct s2io_nic *nic)
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/* Allocation and initialization of RXDs in Rings */
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size = 0;
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for (i = 0; i < config->rx_ring_num; i++) {
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if (config->rx_cfg[i].num_rxd %
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(rxd_count[nic->rxd_mode] + 1)) {
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struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
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struct ring_info *ring = &mac_control->rings[i];
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if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
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DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
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DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
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i);
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DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
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DBG_PRINT(ERR_DBG, "RxDs per Block");
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return FAILURE;
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}
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size += config->rx_cfg[i].num_rxd;
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mac_control->rings[i].block_count =
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config->rx_cfg[i].num_rxd /
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size += rx_cfg->num_rxd;
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ring->block_count = rx_cfg->num_rxd /
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(rxd_count[nic->rxd_mode] + 1 );
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mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
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mac_control->rings[i].block_count;
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ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
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}
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if (nic->rxd_mode == RXD_MODE_1)
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size = (size * (sizeof(struct RxD1)));
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@ -770,26 +788,26 @@ static int init_shared_mem(struct s2io_nic *nic)
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size = (size * (sizeof(struct RxD3)));
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for (i = 0; i < config->rx_ring_num; i++) {
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mac_control->rings[i].rx_curr_get_info.block_index = 0;
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mac_control->rings[i].rx_curr_get_info.offset = 0;
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mac_control->rings[i].rx_curr_get_info.ring_len =
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config->rx_cfg[i].num_rxd - 1;
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mac_control->rings[i].rx_curr_put_info.block_index = 0;
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mac_control->rings[i].rx_curr_put_info.offset = 0;
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mac_control->rings[i].rx_curr_put_info.ring_len =
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config->rx_cfg[i].num_rxd - 1;
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mac_control->rings[i].nic = nic;
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mac_control->rings[i].ring_no = i;
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mac_control->rings[i].lro = lro_enable;
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struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
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struct ring_info *ring = &mac_control->rings[i];
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blk_cnt = config->rx_cfg[i].num_rxd /
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(rxd_count[nic->rxd_mode] + 1);
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ring->rx_curr_get_info.block_index = 0;
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ring->rx_curr_get_info.offset = 0;
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ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
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ring->rx_curr_put_info.block_index = 0;
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ring->rx_curr_put_info.offset = 0;
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ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
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ring->nic = nic;
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ring->ring_no = i;
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ring->lro = lro_enable;
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blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
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/* Allocating all the Rx blocks */
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for (j = 0; j < blk_cnt; j++) {
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struct rx_block_info *rx_blocks;
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int l;
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rx_blocks = &mac_control->rings[i].rx_blocks[j];
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rx_blocks = &ring->rx_blocks[j];
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size = SIZE_OF_BLOCK; //size is always page size
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tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
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&tmp_p_addr);
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}
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/* Interlinking all Rx Blocks */
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for (j = 0; j < blk_cnt; j++) {
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tmp_v_addr =
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mac_control->rings[i].rx_blocks[j].block_virt_addr;
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tmp_v_addr_next =
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mac_control->rings[i].rx_blocks[(j + 1) %
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blk_cnt].block_virt_addr;
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tmp_p_addr =
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mac_control->rings[i].rx_blocks[j].block_dma_addr;
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tmp_p_addr_next =
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mac_control->rings[i].rx_blocks[(j + 1) %
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blk_cnt].block_dma_addr;
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int next = (j + 1) % blk_cnt;
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tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
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tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
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tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
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tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
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pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
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pre_rxd_blk->reserved_2_pNext_RxD_block =
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@ -849,26 +862,28 @@ static int init_shared_mem(struct s2io_nic *nic)
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* and the buffers as well.
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*/
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for (i = 0; i < config->rx_ring_num; i++) {
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blk_cnt = config->rx_cfg[i].num_rxd /
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(rxd_count[nic->rxd_mode]+ 1);
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mac_control->rings[i].ba =
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kmalloc((sizeof(struct buffAdd *) * blk_cnt),
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GFP_KERNEL);
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if (!mac_control->rings[i].ba)
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struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
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struct ring_info *ring = &mac_control->rings[i];
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blk_cnt = rx_cfg->num_rxd /
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(rxd_count[nic->rxd_mode]+ 1);
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ring->ba = kmalloc((sizeof(struct buffAdd *) * blk_cnt),
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GFP_KERNEL);
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if (!ring->ba)
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return -ENOMEM;
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mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
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for (j = 0; j < blk_cnt; j++) {
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int k = 0;
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mac_control->rings[i].ba[j] =
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ring->ba[j] =
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kmalloc((sizeof(struct buffAdd) *
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(rxd_count[nic->rxd_mode] + 1)),
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GFP_KERNEL);
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if (!mac_control->rings[i].ba[j])
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if (!ring->ba[j])
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return -ENOMEM;
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mem_allocated += (sizeof(struct buffAdd) * \
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(rxd_count[nic->rxd_mode] + 1));
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while (k != rxd_count[nic->rxd_mode]) {
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ba = &mac_control->rings[i].ba[j][k];
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ba = &ring->ba[j][k];
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ba->ba_0_org = (void *) kmalloc
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(BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
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@ -952,22 +967,23 @@ static void free_shared_mem(struct s2io_nic *nic)
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lst_per_page = PAGE_SIZE / lst_size;
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for (i = 0; i < config->tx_fifo_num; i++) {
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page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
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lst_per_page);
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struct fifo_info *fifo = &mac_control->fifos[i];
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struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
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page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
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for (j = 0; j < page_num; j++) {
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int mem_blks = (j * lst_per_page);
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if (!mac_control->fifos[i].list_info)
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struct list_info_hold *fli;
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if (!fifo->list_info)
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return;
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if (!mac_control->fifos[i].list_info[mem_blks].
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list_virt_addr)
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fli = &fifo->list_info[mem_blks];
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if (!fli->list_virt_addr)
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break;
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pci_free_consistent(nic->pdev, PAGE_SIZE,
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mac_control->fifos[i].
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list_info[mem_blks].
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list_virt_addr,
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mac_control->fifos[i].
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list_info[mem_blks].
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list_phy_addr);
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fli->list_virt_addr,
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fli->list_phy_addr);
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nic->mac_control.stats_info->sw_stat.mem_freed
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+= PAGE_SIZE;
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}
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@ -986,25 +1002,25 @@ static void free_shared_mem(struct s2io_nic *nic)
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nic->mac_control.stats_info->sw_stat.mem_freed
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+= PAGE_SIZE;
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}
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kfree(mac_control->fifos[i].list_info);
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kfree(fifo->list_info);
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nic->mac_control.stats_info->sw_stat.mem_freed +=
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(nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
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}
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size = SIZE_OF_BLOCK;
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for (i = 0; i < config->rx_ring_num; i++) {
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blk_cnt = mac_control->rings[i].block_count;
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struct ring_info *ring = &mac_control->rings[i];
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blk_cnt = ring->block_count;
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for (j = 0; j < blk_cnt; j++) {
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tmp_v_addr = mac_control->rings[i].rx_blocks[j].
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block_virt_addr;
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tmp_p_addr = mac_control->rings[i].rx_blocks[j].
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block_dma_addr;
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tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
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tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
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if (tmp_v_addr == NULL)
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break;
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pci_free_consistent(nic->pdev, size,
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tmp_v_addr, tmp_p_addr);
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nic->mac_control.stats_info->sw_stat.mem_freed += size;
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kfree(mac_control->rings[i].rx_blocks[j].rxds);
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kfree(ring->rx_blocks[j].rxds);
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nic->mac_control.stats_info->sw_stat.mem_freed +=
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( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
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}
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@ -1013,15 +1029,17 @@ static void free_shared_mem(struct s2io_nic *nic)
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if (nic->rxd_mode == RXD_MODE_3B) {
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/* Freeing buffer storage addresses in 2BUFF mode. */
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for (i = 0; i < config->rx_ring_num; i++) {
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blk_cnt = config->rx_cfg[i].num_rxd /
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(rxd_count[nic->rxd_mode] + 1);
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struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
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struct ring_info *ring = &mac_control->rings[i];
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|
||||
blk_cnt = rx_cfg->num_rxd /
|
||||
(rxd_count[nic->rxd_mode] + 1);
|
||||
for (j = 0; j < blk_cnt; j++) {
|
||||
int k = 0;
|
||||
if (!mac_control->rings[i].ba[j])
|
||||
if (!ring->ba[j])
|
||||
continue;
|
||||
while (k != rxd_count[nic->rxd_mode]) {
|
||||
struct buffAdd *ba =
|
||||
&mac_control->rings[i].ba[j][k];
|
||||
struct buffAdd *ba = &ring->ba[j][k];
|
||||
kfree(ba->ba_0_org);
|
||||
nic->mac_control.stats_info->sw_stat.\
|
||||
mem_freed += (BUF0_LEN + ALIGN_SIZE);
|
||||
|
@ -1030,22 +1048,25 @@ static void free_shared_mem(struct s2io_nic *nic)
|
|||
mem_freed += (BUF1_LEN + ALIGN_SIZE);
|
||||
k++;
|
||||
}
|
||||
kfree(mac_control->rings[i].ba[j]);
|
||||
kfree(ring->ba[j]);
|
||||
nic->mac_control.stats_info->sw_stat.mem_freed +=
|
||||
(sizeof(struct buffAdd) *
|
||||
(rxd_count[nic->rxd_mode] + 1));
|
||||
}
|
||||
kfree(mac_control->rings[i].ba);
|
||||
kfree(ring->ba);
|
||||
nic->mac_control.stats_info->sw_stat.mem_freed +=
|
||||
(sizeof(struct buffAdd *) * blk_cnt);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < nic->config.tx_fifo_num; i++) {
|
||||
if (mac_control->fifos[i].ufo_in_band_v) {
|
||||
struct fifo_info *fifo = &mac_control->fifos[i];
|
||||
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
|
||||
|
||||
if (fifo->ufo_in_band_v) {
|
||||
nic->mac_control.stats_info->sw_stat.mem_freed
|
||||
+= (config->tx_cfg[i].fifo_len * sizeof(u64));
|
||||
kfree(mac_control->fifos[i].ufo_in_band_v);
|
||||
+= (tx_cfg->fifo_len * sizeof(u64));
|
||||
kfree(fifo->ufo_in_band_v);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1339,10 +1360,10 @@ static int init_nic(struct s2io_nic *nic)
|
|||
|
||||
|
||||
for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
|
||||
val64 |=
|
||||
vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
|
||||
13) | vBIT(config->tx_cfg[i].fifo_priority,
|
||||
((j * 32) + 5), 3);
|
||||
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
|
||||
|
||||
val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
|
||||
vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
|
||||
|
||||
if (i == (config->tx_fifo_num - 1)) {
|
||||
if (i % 2 == 0)
|
||||
|
@ -1400,9 +1421,9 @@ static int init_nic(struct s2io_nic *nic)
|
|||
/* Rx DMA intialization. */
|
||||
val64 = 0;
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
val64 |=
|
||||
vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
|
||||
3);
|
||||
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
|
||||
|
||||
val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
|
||||
}
|
||||
writeq(val64, &bar0->rx_queue_priority);
|
||||
|
||||
|
@ -2276,7 +2297,9 @@ static int start_nic(struct s2io_nic *nic)
|
|||
|
||||
/* PRC Initialization and configuration */
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
writeq((u64) ring->rx_blocks[0].block_dma_addr,
|
||||
&bar0->prc_rxd0_n[i]);
|
||||
|
||||
val64 = readq(&bar0->prc_ctrl_n[i]);
|
||||
|
@ -2434,11 +2457,13 @@ static void free_tx_buffers(struct s2io_nic *nic)
|
|||
config = &nic->config;
|
||||
|
||||
for (i = 0; i < config->tx_fifo_num; i++) {
|
||||
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
|
||||
struct fifo_info *fifo = &mac_control->fifos[i];
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
|
||||
for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
|
||||
txdp = (struct TxD *) \
|
||||
mac_control->fifos[i].list_info[j].list_virt_addr;
|
||||
|
||||
spin_lock_irqsave(&fifo->tx_lock, flags);
|
||||
for (j = 0; j < tx_cfg->fifo_len; j++) {
|
||||
txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
|
||||
skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
|
||||
if (skb) {
|
||||
nic->mac_control.stats_info->sw_stat.mem_freed
|
||||
|
@ -2450,9 +2475,9 @@ static void free_tx_buffers(struct s2io_nic *nic)
|
|||
DBG_PRINT(INTR_DBG,
|
||||
"%s:forcibly freeing %d skbs on FIFO%d\n",
|
||||
dev->name, cnt, i);
|
||||
mac_control->fifos[i].tx_curr_get_info.offset = 0;
|
||||
mac_control->fifos[i].tx_curr_put_info.offset = 0;
|
||||
spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
|
||||
fifo->tx_curr_get_info.offset = 0;
|
||||
fifo->tx_curr_put_info.offset = 0;
|
||||
spin_unlock_irqrestore(&fifo->tx_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -2795,14 +2820,16 @@ static void free_rx_buffers(struct s2io_nic *sp)
|
|||
config = &sp->config;
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
for (blk = 0; blk < rx_ring_sz[i]; blk++)
|
||||
free_rxd_blk(sp,i,blk);
|
||||
|
||||
mac_control->rings[i].rx_curr_put_info.block_index = 0;
|
||||
mac_control->rings[i].rx_curr_get_info.block_index = 0;
|
||||
mac_control->rings[i].rx_curr_put_info.offset = 0;
|
||||
mac_control->rings[i].rx_curr_get_info.offset = 0;
|
||||
mac_control->rings[i].rx_bufs_left = 0;
|
||||
ring->rx_curr_put_info.block_index = 0;
|
||||
ring->rx_curr_get_info.block_index = 0;
|
||||
ring->rx_curr_put_info.offset = 0;
|
||||
ring->rx_curr_get_info.offset = 0;
|
||||
ring->rx_bufs_left = 0;
|
||||
DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
|
||||
dev->name, buf_cnt, i);
|
||||
}
|
||||
|
@ -2866,7 +2893,6 @@ static int s2io_poll_msix(struct napi_struct *napi, int budget)
|
|||
static int s2io_poll_inta(struct napi_struct *napi, int budget)
|
||||
{
|
||||
struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
|
||||
struct ring_info *ring;
|
||||
struct config_param *config;
|
||||
struct mac_info *mac_control;
|
||||
int pkts_processed = 0;
|
||||
|
@ -2881,7 +2907,7 @@ static int s2io_poll_inta(struct napi_struct *napi, int budget)
|
|||
return 0;
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
ring = &mac_control->rings[i];
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
ring_pkts_processed = rx_intr_handler(ring, budget);
|
||||
s2io_chk_rx_buffers(nic, ring);
|
||||
pkts_processed += ring_pkts_processed;
|
||||
|
@ -2936,12 +2962,16 @@ static void s2io_netpoll(struct net_device *dev)
|
|||
tx_intr_handler(&mac_control->fifos[i]);
|
||||
|
||||
/* check for received packet and indicate up to network */
|
||||
for (i = 0; i < config->rx_ring_num; i++)
|
||||
rx_intr_handler(&mac_control->rings[i], 0);
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
rx_intr_handler(ring, 0);
|
||||
}
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
|
||||
-ENOMEM) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
|
||||
DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
|
||||
DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
|
||||
break;
|
||||
|
@ -4803,8 +4833,11 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
|
|||
if (reason & GEN_INTR_RXTRAFFIC)
|
||||
writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++)
|
||||
rx_intr_handler(&mac_control->rings[i], 0);
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
rx_intr_handler(ring, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -4825,8 +4858,11 @@ static irqreturn_t s2io_isr(int irq, void *dev_id)
|
|||
* Reallocate the buffers from the interrupt handler itself.
|
||||
*/
|
||||
if (!config->napi) {
|
||||
for (i = 0; i < config->rx_ring_num; i++)
|
||||
s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
s2io_chk_rx_buffers(sp, ring);
|
||||
}
|
||||
}
|
||||
writeq(sp->general_int_mask, &bar0->general_int_mask);
|
||||
readl(&bar0->general_int_status);
|
||||
|
@ -4923,8 +4959,10 @@ static struct net_device_stats *s2io_get_stats(struct net_device *dev)
|
|||
/* collect per-ring rx_packets and rx_bytes */
|
||||
dev->stats.rx_packets = dev->stats.rx_bytes = 0;
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
dev->stats.rx_packets += mac_control->rings[i].rx_packets;
|
||||
dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
dev->stats.rx_packets += ring->rx_packets;
|
||||
dev->stats.rx_bytes += ring->rx_bytes;
|
||||
}
|
||||
|
||||
return (&dev->stats);
|
||||
|
@ -6974,15 +7012,16 @@ static int rxd_owner_bit_reset(struct s2io_nic *sp)
|
|||
size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
blk_cnt = config->rx_cfg[i].num_rxd /
|
||||
(rxd_count[sp->rxd_mode] +1);
|
||||
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] +1);
|
||||
|
||||
for (j = 0; j < blk_cnt; j++) {
|
||||
for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
|
||||
rxdp = mac_control->rings[i].
|
||||
rx_blocks[j].rxds[k].virt_addr;
|
||||
rxdp = ring-> rx_blocks[j].rxds[k].virt_addr;
|
||||
if(sp->rxd_mode == RXD_MODE_3B)
|
||||
ba = &mac_control->rings[i].ba[j][k];
|
||||
ba = &ring->ba[j][k];
|
||||
if (set_rxd_buffer_pointer(sp, rxdp, ba,
|
||||
&skb,(u64 *)&temp0_64,
|
||||
(u64 *)&temp1_64,
|
||||
|
@ -7205,8 +7244,10 @@ static int s2io_card_up(struct s2io_nic * sp)
|
|||
config = &sp->config;
|
||||
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
mac_control->rings[i].mtu = dev->mtu;
|
||||
ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
ring->mtu = dev->mtu;
|
||||
ret = fill_rx_buffers(sp, ring, 1);
|
||||
if (ret) {
|
||||
DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
|
||||
dev->name);
|
||||
|
@ -7215,7 +7256,7 @@ static int s2io_card_up(struct s2io_nic * sp)
|
|||
return -ENOMEM;
|
||||
}
|
||||
DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
|
||||
mac_control->rings[i].rx_bufs_left);
|
||||
ring->rx_bufs_left);
|
||||
}
|
||||
|
||||
/* Initialise napi */
|
||||
|
@ -7875,8 +7916,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
|
||||
config->multiq = dev_multiq;
|
||||
for (i = 0; i < config->tx_fifo_num; i++) {
|
||||
config->tx_cfg[i].fifo_len = tx_fifo_len[i];
|
||||
config->tx_cfg[i].fifo_priority = i;
|
||||
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
|
||||
|
||||
tx_cfg->fifo_len = tx_fifo_len[i];
|
||||
tx_cfg->fifo_priority = i;
|
||||
}
|
||||
|
||||
/* mapping the QoS priority to the configured fifos */
|
||||
|
@ -7890,9 +7933,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
|
||||
config->tx_intr_type = TXD_INT_TYPE_UTILZ;
|
||||
for (i = 0; i < config->tx_fifo_num; i++) {
|
||||
config->tx_cfg[i].f_no_snoop =
|
||||
(NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
|
||||
if (config->tx_cfg[i].fifo_len < 65) {
|
||||
struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
|
||||
|
||||
tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
|
||||
if (tx_cfg->fifo_len < 65) {
|
||||
config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
|
||||
break;
|
||||
}
|
||||
|
@ -7903,20 +7947,23 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
/* Rx side parameters. */
|
||||
config->rx_ring_num = rx_ring_num;
|
||||
for (i = 0; i < config->rx_ring_num; i++) {
|
||||
config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
|
||||
(rxd_count[sp->rxd_mode] + 1);
|
||||
config->rx_cfg[i].ring_priority = i;
|
||||
mac_control->rings[i].rx_bufs_left = 0;
|
||||
mac_control->rings[i].rxd_mode = sp->rxd_mode;
|
||||
mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
|
||||
mac_control->rings[i].pdev = sp->pdev;
|
||||
mac_control->rings[i].dev = sp->dev;
|
||||
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
|
||||
rx_cfg->ring_priority = i;
|
||||
ring->rx_bufs_left = 0;
|
||||
ring->rxd_mode = sp->rxd_mode;
|
||||
ring->rxd_count = rxd_count[sp->rxd_mode];
|
||||
ring->pdev = sp->pdev;
|
||||
ring->dev = sp->dev;
|
||||
}
|
||||
|
||||
for (i = 0; i < rx_ring_num; i++) {
|
||||
config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
|
||||
config->rx_cfg[i].f_no_snoop =
|
||||
(NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
|
||||
struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
|
||||
|
||||
rx_cfg->ring_org = RING_ORG_BUFF1;
|
||||
rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
|
||||
}
|
||||
|
||||
/* Setting Mac Control parameters */
|
||||
|
@ -8015,9 +8062,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
}
|
||||
|
||||
if (config->intr_type == MSI_X) {
|
||||
for (i = 0; i < config->rx_ring_num ; i++)
|
||||
netif_napi_add(dev, &mac_control->rings[i].napi,
|
||||
s2io_poll_msix, 64);
|
||||
for (i = 0; i < config->rx_ring_num ; i++) {
|
||||
struct ring_info *ring = &mac_control->rings[i];
|
||||
|
||||
netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
|
||||
}
|
||||
} else {
|
||||
netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
|
||||
}
|
||||
|
@ -8089,8 +8138,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
sp->state = 0;
|
||||
|
||||
/* Initialize spinlocks */
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
spin_lock_init(&mac_control->fifos[i].tx_lock);
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++) {
|
||||
struct fifo_info *fifo = &mac_control->fifos[i];
|
||||
|
||||
spin_lock_init(&fifo->tx_lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* SXE-002: Configure link and activity LED to init state
|
||||
|
@ -8165,8 +8217,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
break;
|
||||
}
|
||||
if (sp->config.multiq) {
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
mac_control->fifos[i].multiq = config->multiq;
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++) {
|
||||
struct fifo_info *fifo = &mac_control->fifos[i];
|
||||
|
||||
fifo->multiq = config->multiq;
|
||||
}
|
||||
DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
|
||||
dev->name);
|
||||
} else
|
||||
|
|
Loading…
Reference in a new issue