Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP2xxx clock: set up clockdomain pointer in struct clk OMAP: Fix race condition with autodeps omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop omap: Initialization of SDRC params on Zoom2 omap: RX-51: Drop I2C-1 speed to 2200 omap: SDMA: Fixing bug in omap_dma_set_global_params() omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfig
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commit
13e356c977
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@ -969,7 +969,6 @@ CONFIG_USB_ETH_RNDIS=y
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#
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CONFIG_USB_OTG_UTILS=y
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# CONFIG_USB_GPIO_VBUS is not set
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# CONFIG_ISP1301_OMAP is not set
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CONFIG_TWL4030_USB=y
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# CONFIG_NOP_USB_XCEIV is not set
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CONFIG_MMC=y
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@ -444,7 +444,7 @@ static int __init rx51_i2c_init(void)
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rx51_twldata.vaux3 = &rx51_vaux3_cam;
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rx51_twldata.vmmc2 = &rx51_vmmc2;
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}
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omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
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omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
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ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
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omap_register_i2c_bus(2, 100, NULL, 0);
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omap_register_i2c_bus(3, 400, NULL, 0);
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@ -25,6 +25,7 @@
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#include <mach/keypad.h>
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#include "mmc-twl4030.h"
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#include "sdram-micron-mt46h32m32lf-6.h"
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/* Zoom2 has Qwerty keyboard*/
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static int board_keymap[] = {
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@ -213,7 +214,8 @@ static void __init omap_zoom2_init_irq(void)
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{
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omap_board_config = zoom2_config;
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omap_board_config_size = ARRAY_SIZE(zoom2_config);
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omap2_init_common_hw(NULL, NULL);
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
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mt46h32m32lf6_sdrc_params);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -769,6 +769,7 @@ int __init omap2_clk_init(void)
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if (c->cpu & cpu_mask) {
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clkdev_add(&c->lk);
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clk_register(c->lk.clk);
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omap2_init_clk_clkdm(c->lk.clk);
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}
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/* Check the MPU rate set by bootloader */
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@ -137,6 +137,36 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
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}
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}
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/*
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* _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
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* @clkdm: struct clockdomain *
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* @enable: int 0 to disable, 1 to enable
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*
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* Internal helper for actually switching the bit that controls hwsup
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* idle transitions for clkdm.
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*/
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static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
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{
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u32 v;
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if (cpu_is_omap24xx()) {
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if (enable)
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v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
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else
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v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
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} else if (cpu_is_omap34xx()) {
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if (enable)
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v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
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else
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v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
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} else {
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BUG();
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}
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cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
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v << __ffs(clkdm->clktrctrl_mask),
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clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
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}
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static struct clockdomain *_clkdm_lookup(const char *name)
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{
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@ -456,8 +486,6 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
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*/
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void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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u32 v;
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if (!clkdm)
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return;
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@ -473,18 +501,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_add_autodeps(clkdm);
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if (cpu_is_omap24xx())
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v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
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else if (cpu_is_omap34xx())
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v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
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else
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BUG();
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cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
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v << __ffs(clkdm->clktrctrl_mask),
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clkdm->pwrdm.ptr->prcm_offs,
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CM_CLKSTCTRL);
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_omap2_clkdm_set_hwsup(clkdm, 1);
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pwrdm_clkdm_state_switch(clkdm);
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}
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@ -500,8 +517,6 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
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*/
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void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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u32 v;
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if (!clkdm)
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return;
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@ -514,16 +529,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
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pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
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clkdm->name);
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if (cpu_is_omap24xx())
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v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
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else if (cpu_is_omap34xx())
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v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
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else
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BUG();
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cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
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v << __ffs(clkdm->clktrctrl_mask),
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clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
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_omap2_clkdm_set_hwsup(clkdm, 0);
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_del_autodeps(clkdm);
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@ -569,10 +575,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
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v = omap2_clkdm_clktrctrl_read(clkdm);
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if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
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(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
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(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
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/* Disable HW transitions when we are changing deps */
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_omap2_clkdm_set_hwsup(clkdm, 0);
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_clkdm_add_autodeps(clkdm);
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else
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_omap2_clkdm_set_hwsup(clkdm, 1);
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} else {
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omap2_clkdm_wakeup(clkdm);
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}
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pwrdm_wait_transition(clkdm->pwrdm.ptr);
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pwrdm_clkdm_state_switch(clkdm);
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@ -623,10 +633,14 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
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v = omap2_clkdm_clktrctrl_read(clkdm);
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if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
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(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
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(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
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/* Disable HW transitions when we are changing deps */
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_omap2_clkdm_set_hwsup(clkdm, 0);
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_clkdm_del_autodeps(clkdm);
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else
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_omap2_clkdm_set_hwsup(clkdm, 1);
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} else {
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omap2_clkdm_sleep(clkdm);
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}
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pwrdm_clkdm_state_switch(clkdm);
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@ -829,10 +829,10 @@ EXPORT_SYMBOL(omap_free_dma);
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*
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* @param arb_rate
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* @param max_fifo_depth
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* @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
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* DMA_THREAD_RESERVE_ONET
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* DMA_THREAD_RESERVE_TWOT
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* DMA_THREAD_RESERVE_THREET
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* @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
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* DMA_THREAD_RESERVE_ONET
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* DMA_THREAD_RESERVE_TWOT
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* DMA_THREAD_RESERVE_THREET
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*/
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void
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omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
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@ -844,11 +844,14 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
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return;
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}
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if (max_fifo_depth == 0)
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max_fifo_depth = 1;
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if (arb_rate == 0)
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arb_rate = 1;
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reg = (arb_rate & 0xff) << 16;
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reg |= (0xff & max_fifo_depth);
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reg = 0xff & max_fifo_depth;
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reg |= (0x3 & tparams) << 12;
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reg |= (arb_rate & 0xff) << 16;
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dma_write(reg, GCR);
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}
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@ -595,7 +595,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
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rx &= 1;
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if (cpu_is_omap2430() || cpu_is_omap34xx()) {
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w = OMAP_MCBSP_READ(io_base, RCCR);
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w |= (tx ? RDISABLE : 0);
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w |= (rx ? RDISABLE : 0);
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OMAP_MCBSP_WRITE(io_base, RCCR, w);
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}
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w = OMAP_MCBSP_READ(io_base, SPCR1);
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