perf/x86: fix PEBS issues on Intel Atom/Core2
This patch fixes broken PEBS support on Intel Atom and Core2
due to wrong pointer arithmetic in intel_pmu_drain_pebs_core().
The get_next_pebs_record_by_bit() was called on PEBS format fmt0
which does not use the pebs_record_nhm layout.
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: kan.liang@intel.com
Fixes: 21509084f9
("perf/x86/intel: Handle multiple records in the PEBS buffer")
Link: http://lkml.kernel.org/r/1449182000-31524-3-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
hifive-unleashed-5.1
parent
6fc2e83077
commit
1424a09a9e
|
@ -1106,6 +1106,13 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
|
|||
void *at;
|
||||
u64 pebs_status;
|
||||
|
||||
/*
|
||||
* fmt0 does not have a status bitfield (does not use
|
||||
* perf_record_nhm format)
|
||||
*/
|
||||
if (x86_pmu.intel_cap.pebs_format < 1)
|
||||
return base;
|
||||
|
||||
if (base == NULL)
|
||||
return NULL;
|
||||
|
||||
|
@ -1191,7 +1198,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
|
|||
if (!event->attr.precise_ip)
|
||||
return;
|
||||
|
||||
n = (top - at) / x86_pmu.pebs_record_size;
|
||||
n = top - at;
|
||||
if (n <= 0)
|
||||
return;
|
||||
|
||||
|
|
Loading…
Reference in New Issue