drm/i915: Invalidate media caches on gen7
In the gen7 pipe control there is an extra bit to flush the media caches, so let's set it during cache invalidation flushes. v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec. Cc: Simon Farnsworth <simon@farnz.org.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -395,6 +395,7 @@
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#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
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#define PIPE_CONTROL_CS_STALL (1<<20)
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#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
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#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
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#define PIPE_CONTROL_DEPTH_STALL (1<<13)
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@ -362,6 +362,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
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flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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