drm/amd/display: add functionality to grab DPRX CRC entries.
[Why] We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode. [How] Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc. Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>alistair/sunxi64-5.4-dsi
Dingchen Zhang
Alex Deucher
parent
2425347697
commit
14b2584636
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@ -3665,7 +3665,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
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state->abm_level = cur->abm_level;
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state->vrr_supported = cur->vrr_supported;
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state->freesync_config = cur->freesync_config;
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state->crc_enabled = cur->crc_enabled;
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state->crc_src = cur->crc_src;
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state->cm_has_degamma = cur->cm_has_degamma;
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state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
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@ -5975,6 +5975,7 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
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struct drm_crtc *crtc;
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struct drm_crtc_state *old_crtc_state, *new_crtc_state;
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int i;
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enum amdgpu_dm_pipe_crc_source source;
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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@ -6000,9 +6001,13 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
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#ifdef CONFIG_DEBUG_FS
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/* The stream has changed so CRC capture needs to re-enabled. */
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if (dm_new_crtc_state->crc_enabled) {
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dm_new_crtc_state->crc_enabled = false;
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amdgpu_dm_crtc_set_crc_source(crtc, "auto");
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source = dm_new_crtc_state->crc_src;
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if (amdgpu_dm_is_valid_crc_source(source)) {
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dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
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if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC)
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amdgpu_dm_crtc_set_crc_source(crtc, "crtc");
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else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)
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amdgpu_dm_crtc_set_crc_source(crtc, "dprx");
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}
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#endif
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}
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@ -6058,7 +6063,7 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
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* Drop the extra vblank reference added by CRC
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* capture if applicable.
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*/
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if (dm_new_crtc_state->crc_enabled)
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if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src))
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drm_crtc_vblank_put(crtc);
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/*
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@ -6066,7 +6071,7 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
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* still a stream for the CRTC.
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*/
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if (!dm_new_crtc_state->stream)
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dm_new_crtc_state->crc_enabled = false;
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dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
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manage_dm_interrupts(adev, acrtc, false);
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}
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@ -50,6 +50,7 @@
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#include "irq_types.h"
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#include "signal_types.h"
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#include "amdgpu_dm_crc.h"
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/* Forward declarations */
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struct amdgpu_device;
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@ -313,7 +314,7 @@ struct dm_crtc_state {
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bool interrupts_enabled;
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int crc_skip_count;
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bool crc_enabled;
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enum amdgpu_dm_pipe_crc_source crc_src;
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bool freesync_timing_changed;
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bool freesync_vrr_info_changed;
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@ -380,19 +381,6 @@ void dm_restore_drm_connector_state(struct drm_device *dev,
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void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
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struct edid *edid);
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/* amdgpu_dm_crc.c */
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#ifdef CONFIG_DEBUG_FS
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int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
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int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
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const char *src_name,
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size_t *values_cnt);
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void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
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#else
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#define amdgpu_dm_crtc_set_crc_source NULL
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#define amdgpu_dm_crtc_verify_crc_source NULL
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#define amdgpu_dm_crtc_handle_crc_irq(x)
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#endif
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#define MAX_COLOR_LUT_ENTRIES 4096
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/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
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#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
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@ -30,19 +30,14 @@
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#include "amdgpu_dm.h"
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#include "dc.h"
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enum amdgpu_dm_pipe_crc_source {
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AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
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AMDGPU_DM_PIPE_CRC_SOURCE_AUTO,
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AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
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AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
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};
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static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
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{
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if (!source || !strcmp(source, "none"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
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if (!strcmp(source, "auto"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_AUTO;
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if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
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if (!strcmp(source, "dprx"))
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return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
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return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
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}
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@ -68,7 +63,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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struct amdgpu_device *adev = crtc->dev->dev_private;
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struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
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struct dc_stream_state *stream_state = crtc_state->stream;
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bool enable;
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struct amdgpu_dm_connector *aconn;
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struct drm_dp_aux *aux = NULL;
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bool enable = false;
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bool enabled = false;
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enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
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@ -83,13 +81,42 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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return -EINVAL;
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}
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enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
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enable = amdgpu_dm_is_valid_crc_source(source);
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mutex_lock(&adev->dm.dc_lock);
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if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
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enable, enable)) {
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mutex_unlock(&adev->dm.dc_lock);
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return -EINVAL;
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/*
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* USER REQ SRC | CURRENT SRC | BEHAVIOR
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* -----------------------------
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* None | None | Do nothing
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* None | CRTC | Disable CRTC CRC
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* None | DPRX | Disable DPRX CRC, need 'aux'
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* CRTC | XXXX | Enable CRTC CRC, configure DC strm
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* DPRX | XXXX | Enable DPRX CRC, need 'aux'
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*/
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if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX ||
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(source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
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crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)) {
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aconn = stream_state->link->priv;
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if (!aconn) {
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DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
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mutex_unlock(&adev->dm.dc_lock);
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return -EINVAL;
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}
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aux = &aconn->dm_dp_aux.aux;
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if (!aux) {
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DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
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mutex_unlock(&adev->dm.dc_lock);
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return -EINVAL;
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}
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} else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
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if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
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enable, enable)) {
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mutex_unlock(&adev->dm.dc_lock);
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return -EINVAL;
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}
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}
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/* When enabling CRC, we should also disable dithering. */
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@ -103,12 +130,26 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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* Reading the CRC requires the vblank interrupt handler to be
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* enabled. Keep a reference until CRC capture stops.
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*/
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if (!crtc_state->crc_enabled && enable)
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enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
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if (!enabled && enable) {
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drm_crtc_vblank_get(crtc);
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else if (crtc_state->crc_enabled && !enable)
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if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
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if (drm_dp_start_crc(aux, crtc)) {
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DRM_DEBUG_DRIVER("dp start crc failed\n");
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return -EINVAL;
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}
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}
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} else if (enabled && !enable) {
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drm_crtc_vblank_put(crtc);
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if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
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if (drm_dp_stop_crc(aux)) {
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DRM_DEBUG_DRIVER("dp stop crc failed\n");
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return -EINVAL;
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}
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}
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}
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crtc_state->crc_enabled = enable;
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crtc_state->crc_src = source;
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/* Reset crc_skipped on dm state */
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crtc_state->crc_skip_count = 0;
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@ -135,7 +176,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
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stream_state = crtc_state->stream;
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/* Early return if CRC capture is not enabled. */
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if (!crtc_state->crc_enabled)
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if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
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return;
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/*
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@ -149,10 +190,12 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
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return;
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}
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if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
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&crcs[0], &crcs[1], &crcs[2]))
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return;
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if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
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if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
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&crcs[0], &crcs[1], &crcs[2]))
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return;
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drm_crtc_add_crc_entry(crtc, true,
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drm_crtc_accurate_vblank_count(crtc), crcs);
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drm_crtc_add_crc_entry(crtc, true,
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drm_crtc_accurate_vblank_count(crtc), crcs);
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}
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}
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@ -0,0 +1,56 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
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#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
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enum amdgpu_dm_pipe_crc_source {
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AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
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AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
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AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
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AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
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AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
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};
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static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
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{
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return (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
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(source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX);
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}
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/* amdgpu_dm_crc.c */
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#ifdef CONFIG_DEBUG_FS
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int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
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int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
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const char *src_name,
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size_t *values_cnt);
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void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
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#else
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#define amdgpu_dm_crtc_set_crc_source NULL
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#define amdgpu_dm_crtc_verify_crc_source NULL
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#define amdgpu_dm_crtc_handle_crc_irq(x)
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#endif
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#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
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