Merge branch 'drm-radeon-evergreen-accel' into drm-core-next
* drm-radeon-evergreen-accel: drm/radeon: fix cypress firmware typo. drm/radeon/kms/evergreen: add hpd support drm/radeon/kms/evergreen: implement irq support drm/radeon/kms/evergreen: setup and enable the CP drm/radeon/kms/evergreen: implement gfx init drm/radeon/kms/evergreen: add soft reset function drm/radeon/kms/evergreen: add gart support drm/radeon/kms: add support for evergreen power tables drm/radeon/kms: update atombios.h power tables for evergreen
This commit is contained in:
Dave Airlie
commit
153549b8b6
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@ -5742,6 +5742,9 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
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#define ATOM_PP_THERMALCONTROLLER_RV6xx 7
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#define ATOM_PP_THERMALCONTROLLER_RV770 8
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#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
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#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11
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#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
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#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
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typedef struct _ATOM_PPLIB_STATE
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{
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@ -5749,6 +5752,26 @@ typedef struct _ATOM_PPLIB_STATE
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UCHAR ucClockStateIndices[1]; // variable-sized
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} ATOM_PPLIB_STATE;
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typedef struct _ATOM_PPLIB_FANTABLE
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{
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UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
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UCHAR ucTHyst; // Temperature hysteresis. Integer.
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USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
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USHORT usTMed; // The middle temperature where we change slopes.
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USHORT usTHigh; // The high point above TMed for adjusting the second slope.
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USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments).
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USHORT usPWMMed; // The PWM value (in percent) at TMed.
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USHORT usPWMHigh; // The PWM value at THigh.
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} ATOM_PPLIB_FANTABLE;
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typedef struct _ATOM_PPLIB_EXTENDEDHEADER
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{
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USHORT usSize;
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ULONG ulMaxEngineClock; // For Overdrive.
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ULONG ulMaxMemoryClock; // For Overdrive.
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// Add extra system parameters here, always adjust size to include all fields.
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} ATOM_PPLIB_EXTENDEDHEADER;
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//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
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#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
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#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
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@ -5762,6 +5785,12 @@ typedef struct _ATOM_PPLIB_STATE
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#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
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#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
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#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
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#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
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#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
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#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
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#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC.
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#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
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#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
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typedef struct _ATOM_PPLIB_POWERPLAYTABLE
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{
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@ -5797,6 +5826,21 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE
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} ATOM_PPLIB_POWERPLAYTABLE;
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typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
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{
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ATOM_PPLIB_POWERPLAYTABLE basicTable;
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UCHAR ucNumCustomThermalPolicy;
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USHORT usCustomThermalPolicyArrayOffset;
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}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
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typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
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{
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ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
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USHORT usFormatID; // To be used ONLY by PPGen.
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USHORT usFanTableOffset;
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USHORT usExtendendedHeaderOffset;
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} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
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//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
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#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
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#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
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@ -5816,7 +5860,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE
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#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
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#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
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#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
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// remaining 3 bits are reserved
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#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000
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#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
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#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
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//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
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#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
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@ -5840,9 +5886,15 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE
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#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
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#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
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#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
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#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
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#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
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//memory related flags
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#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000
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//M3 Arb //2bits, current 3 sets of parameters in total
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#define ATOM_PPLIB_M3ARB_MASK 0x00060000
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#define ATOM_PPLIB_M3ARB_SHIFT 17
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// Contained in an array starting at the offset
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// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
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@ -5860,6 +5912,9 @@ typedef struct _ATOM_PPLIB_NONCLOCK_INFO
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// Contained in an array starting at the offset
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// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
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// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
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#define ATOM_PPLIB_NONCLOCKINFO_VER1 12
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#define ATOM_PPLIB_NONCLOCKINFO_VER2 24
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typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
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{
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USHORT usEngineClockLow;
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@ -5882,6 +5937,23 @@ typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
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#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
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#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
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#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
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#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0).
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typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
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{
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USHORT usEngineClockLow;
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UCHAR ucEngineClockHigh;
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USHORT usMemoryClockLow;
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UCHAR ucMemoryClockHigh;
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USHORT usVDDC;
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USHORT usVDDCI;
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USHORT usUnused;
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ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
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} ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
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typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
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@ -249,17 +249,13 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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if (ASIC_IS_DCE3(rdev))
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atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
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atombios_blank_crtc(crtc, ATOM_DISABLE);
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/* XXX re-enable when interrupt support is added */
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if (!ASIC_IS_DCE4(rdev))
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drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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radeon_crtc_load_lut(crtc);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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/* XXX re-enable when interrupt support is added */
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if (!ASIC_IS_DCE4(rdev))
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drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
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drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
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atombios_blank_crtc(crtc, ATOM_ENABLE);
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if (ASIC_IS_DCE3(rdev))
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atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
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File diff suppressed because it is too large
Load diff
556
drivers/gpu/drm/radeon/evergreend.h
Normal file
556
drivers/gpu/drm/radeon/evergreend.h
Normal file
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@ -0,0 +1,556 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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||||
* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef EVERGREEND_H
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#define EVERGREEND_H
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#define EVERGREEN_MAX_SH_GPRS 256
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#define EVERGREEN_MAX_TEMP_GPRS 16
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#define EVERGREEN_MAX_SH_THREADS 256
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#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
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#define EVERGREEN_MAX_FRC_EOV_CNT 16384
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#define EVERGREEN_MAX_BACKENDS 8
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#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
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#define EVERGREEN_MAX_SIMDS 16
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#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
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#define EVERGREEN_MAX_PIPES 8
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#define EVERGREEN_MAX_PIPES_MASK 0xFF
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#define EVERGREEN_MAX_LDS_NUM 0xFFFF
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/* Registers */
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#define RCU_IND_INDEX 0x100
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#define RCU_IND_DATA 0x104
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#define GRBM_GFX_INDEX 0x802C
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SE_INDEX(x) ((x) << 16)
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#define INSTANCE_BROADCAST_WRITES (1 << 30)
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#define SE_BROADCAST_WRITES (1 << 31)
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#define RLC_GFX_INDEX 0x3fC4
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#define CC_GC_SHADER_PIPE_CONFIG 0x8950
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#define WRITE_DIS (1 << 0)
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#define CC_RB_BACKEND_DISABLE 0x98F4
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#define BACKEND_DISABLE(x) ((x) << 16)
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#define GB_ADDR_CONFIG 0x98F8
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#define NUM_PIPES(x) ((x) << 0)
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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
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#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
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#define NUM_SHADER_ENGINES(x) ((x) << 12)
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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
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#define NUM_GPUS(x) ((x) << 20)
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#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
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#define ROW_SIZE(x) ((x) << 28)
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#define GB_BACKEND_MAP 0x98FC
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#define DMIF_ADDR_CONFIG 0xBD4
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#define HDP_ADDR_CONFIG 0x2F48
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#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
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#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
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#define CGTS_SYS_TCC_DISABLE 0x3F90
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#define CGTS_TCC_DISABLE 0x9148
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#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
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#define CGTS_USER_TCC_DISABLE 0x914C
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|
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#define CONFIG_MEMSIZE 0x5428
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|
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#define CP_ME_CNTL 0x86D8
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#define CP_ME_HALT (1 << 28)
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#define CP_PFP_HALT (1 << 26)
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#define CP_ME_RAM_DATA 0xC160
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#define CP_ME_RAM_RADDR 0xC158
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#define CP_ME_RAM_WADDR 0xC15C
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#define CP_MEQ_THRESHOLDS 0x8764
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#define STQ_SPLIT(x) ((x) << 0)
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#define CP_PERFMON_CNTL 0x87FC
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#define CP_PFP_UCODE_ADDR 0xC150
|
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#define CP_PFP_UCODE_DATA 0xC154
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#define CP_QUEUE_THRESHOLDS 0x8760
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#define ROQ_IB1_START(x) ((x) << 0)
|
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#define ROQ_IB2_START(x) ((x) << 8)
|
||||
#define CP_RB_BASE 0xC100
|
||||
#define CP_RB_CNTL 0xC104
|
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#define RB_BUFSZ(x) ((x) << 0)
|
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#define RB_BLKSZ(x) ((x) << 8)
|
||||
#define RB_NO_UPDATE (1 << 27)
|
||||
#define RB_RPTR_WR_ENA (1 << 31)
|
||||
#define BUF_SWAP_32BIT (2 << 16)
|
||||
#define CP_RB_RPTR 0x8700
|
||||
#define CP_RB_RPTR_ADDR 0xC10C
|
||||
#define CP_RB_RPTR_ADDR_HI 0xC110
|
||||
#define CP_RB_RPTR_WR 0xC108
|
||||
#define CP_RB_WPTR 0xC114
|
||||
#define CP_RB_WPTR_ADDR 0xC118
|
||||
#define CP_RB_WPTR_ADDR_HI 0xC11C
|
||||
#define CP_RB_WPTR_DELAY 0x8704
|
||||
#define CP_SEM_WAIT_TIMER 0x85BC
|
||||
#define CP_DEBUG 0xC1FC
|
||||
|
||||
|
||||
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
|
||||
#define INACTIVE_QD_PIPES(x) ((x) << 8)
|
||||
#define INACTIVE_QD_PIPES_MASK 0x0000FF00
|
||||
#define INACTIVE_SIMDS(x) ((x) << 16)
|
||||
#define INACTIVE_SIMDS_MASK 0x00FF0000
|
||||
|
||||
#define GRBM_CNTL 0x8000
|
||||
#define GRBM_READ_TIMEOUT(x) ((x) << 0)
|
||||
#define GRBM_SOFT_RESET 0x8020
|
||||
#define SOFT_RESET_CP (1 << 0)
|
||||
#define SOFT_RESET_CB (1 << 1)
|
||||
#define SOFT_RESET_DB (1 << 3)
|
||||
#define SOFT_RESET_PA (1 << 5)
|
||||
#define SOFT_RESET_SC (1 << 6)
|
||||
#define SOFT_RESET_SPI (1 << 8)
|
||||
#define SOFT_RESET_SH (1 << 9)
|
||||
#define SOFT_RESET_SX (1 << 10)
|
||||
#define SOFT_RESET_TC (1 << 11)
|
||||
#define SOFT_RESET_TA (1 << 12)
|
||||
#define SOFT_RESET_VC (1 << 13)
|
||||
#define SOFT_RESET_VGT (1 << 14)
|
||||
|
||||
#define GRBM_STATUS 0x8010
|
||||
#define CMDFIFO_AVAIL_MASK 0x0000000F
|
||||
#define SRBM_RQ_PENDING (1 << 5)
|
||||
#define CF_RQ_PENDING (1 << 7)
|
||||
#define PF_RQ_PENDING (1 << 8)
|
||||
#define GRBM_EE_BUSY (1 << 10)
|
||||
#define SX_CLEAN (1 << 11)
|
||||
#define DB_CLEAN (1 << 12)
|
||||
#define CB_CLEAN (1 << 13)
|
||||
#define TA_BUSY (1 << 14)
|
||||
#define VGT_BUSY_NO_DMA (1 << 16)
|
||||
#define VGT_BUSY (1 << 17)
|
||||
#define SX_BUSY (1 << 20)
|
||||
#define SH_BUSY (1 << 21)
|
||||
#define SPI_BUSY (1 << 22)
|
||||
#define SC_BUSY (1 << 24)
|
||||
#define PA_BUSY (1 << 25)
|
||||
#define DB_BUSY (1 << 26)
|
||||
#define CP_COHERENCY_BUSY (1 << 28)
|
||||
#define CP_BUSY (1 << 29)
|
||||
#define CB_BUSY (1 << 30)
|
||||
#define GUI_ACTIVE (1 << 31)
|
||||
#define GRBM_STATUS_SE0 0x8014
|
||||
#define GRBM_STATUS_SE1 0x8018
|
||||
#define SE_SX_CLEAN (1 << 0)
|
||||
#define SE_DB_CLEAN (1 << 1)
|
||||
#define SE_CB_CLEAN (1 << 2)
|
||||
#define SE_TA_BUSY (1 << 25)
|
||||
#define SE_SX_BUSY (1 << 26)
|
||||
#define SE_SPI_BUSY (1 << 27)
|
||||
#define SE_SH_BUSY (1 << 28)
|
||||
#define SE_SC_BUSY (1 << 29)
|
||||
#define SE_DB_BUSY (1 << 30)
|
||||
#define SE_CB_BUSY (1 << 31)
|
||||
|
||||
#define HDP_HOST_PATH_CNTL 0x2C00
|
||||
#define HDP_NONSURFACE_BASE 0x2C04
|
||||
#define HDP_NONSURFACE_INFO 0x2C08
|
||||
#define HDP_NONSURFACE_SIZE 0x2C0C
|
||||
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
|
||||
#define HDP_TILING_CONFIG 0x2F3C
|
||||
|
||||
#define MC_SHARED_CHMAP 0x2004
|
||||
#define NOOFCHAN_SHIFT 12
|
||||
#define NOOFCHAN_MASK 0x00003000
|
||||
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
#define NOOFBANK_MASK 0x00000003
|
||||
#define NOOFRANK_SHIFT 2
|
||||
#define NOOFRANK_MASK 0x00000004
|
||||
#define NOOFROWS_SHIFT 3
|
||||
#define NOOFROWS_MASK 0x00000038
|
||||
#define NOOFCOLS_SHIFT 6
|
||||
#define NOOFCOLS_MASK 0x000000C0
|
||||
#define CHANSIZE_SHIFT 8
|
||||
#define CHANSIZE_MASK 0x00000100
|
||||
#define BURSTLENGTH_SHIFT 9
|
||||
#define BURSTLENGTH_MASK 0x00000200
|
||||
#define CHANSIZE_OVERRIDE (1 << 11)
|
||||
#define MC_VM_AGP_TOP 0x2028
|
||||
#define MC_VM_AGP_BOT 0x202C
|
||||
#define MC_VM_AGP_BASE 0x2030
|
||||
#define MC_VM_FB_LOCATION 0x2024
|
||||
#define MC_VM_MB_L1_TLB0_CNTL 0x2234
|
||||
#define MC_VM_MB_L1_TLB1_CNTL 0x2238
|
||||
#define MC_VM_MB_L1_TLB2_CNTL 0x223C
|
||||
#define MC_VM_MB_L1_TLB3_CNTL 0x2240
|
||||
#define ENABLE_L1_TLB (1 << 0)
|
||||
#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
|
||||
#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
|
||||
#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
|
||||
#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
|
||||
#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
|
||||
#define MC_VM_MD_L1_TLB0_CNTL 0x2654
|
||||
#define MC_VM_MD_L1_TLB1_CNTL 0x2658
|
||||
#define MC_VM_MD_L1_TLB2_CNTL 0x265C
|
||||
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
|
||||
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
|
||||
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
|
||||
|
||||
#define PA_CL_ENHANCE 0x8A14
|
||||
#define CLIP_VTX_REORDER_ENA (1 << 0)
|
||||
#define NUM_CLIP_SEQ(x) ((x) << 1)
|
||||
#define PA_SC_AA_CONFIG 0x28C04
|
||||
#define PA_SC_CLIPRECT_RULE 0x2820C
|
||||
#define PA_SC_EDGERULE 0x28230
|
||||
#define PA_SC_FIFO_SIZE 0x8BCC
|
||||
#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
|
||||
#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
|
||||
#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
|
||||
#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
|
||||
#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
|
||||
#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
|
||||
#define PA_SC_LINE_STIPPLE 0x28A0C
|
||||
#define PA_SC_LINE_STIPPLE_STATE 0x8B10
|
||||
|
||||
#define SCRATCH_REG0 0x8500
|
||||
#define SCRATCH_REG1 0x8504
|
||||
#define SCRATCH_REG2 0x8508
|
||||
#define SCRATCH_REG3 0x850C
|
||||
#define SCRATCH_REG4 0x8510
|
||||
#define SCRATCH_REG5 0x8514
|
||||
#define SCRATCH_REG6 0x8518
|
||||
#define SCRATCH_REG7 0x851C
|
||||
#define SCRATCH_UMSK 0x8540
|
||||
#define SCRATCH_ADDR 0x8544
|
||||
|
||||
#define SMX_DC_CTL0 0xA020
|
||||
#define USE_HASH_FUNCTION (1 << 0)
|
||||
#define NUMBER_OF_SETS(x) ((x) << 1)
|
||||
#define FLUSH_ALL_ON_EVENT (1 << 10)
|
||||
#define STALL_ON_EVENT (1 << 11)
|
||||
#define SMX_EVENT_CTL 0xA02C
|
||||
#define ES_FLUSH_CTL(x) ((x) << 0)
|
||||
#define GS_FLUSH_CTL(x) ((x) << 3)
|
||||
#define ACK_FLUSH_CTL(x) ((x) << 6)
|
||||
#define SYNC_FLUSH_CTL (1 << 8)
|
||||
|
||||
#define SPI_CONFIG_CNTL 0x9100
|
||||
#define GPR_WRITE_PRIORITY(x) ((x) << 0)
|
||||
#define SPI_CONFIG_CNTL_1 0x913C
|
||||
#define VTX_DONE_DELAY(x) ((x) << 0)
|
||||
#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
|
||||
#define SPI_INPUT_Z 0x286D8
|
||||
#define SPI_PS_IN_CONTROL_0 0x286CC
|
||||
#define NUM_INTERP(x) ((x)<<0)
|
||||
#define POSITION_ENA (1<<8)
|
||||
#define POSITION_CENTROID (1<<9)
|
||||
#define POSITION_ADDR(x) ((x)<<10)
|
||||
#define PARAM_GEN(x) ((x)<<15)
|
||||
#define PARAM_GEN_ADDR(x) ((x)<<19)
|
||||
#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
|
||||
#define PERSP_GRADIENT_ENA (1<<28)
|
||||
#define LINEAR_GRADIENT_ENA (1<<29)
|
||||
#define POSITION_SAMPLE (1<<30)
|
||||
#define BARYC_AT_SAMPLE_ENA (1<<31)
|
||||
|
||||
#define SQ_CONFIG 0x8C00
|
||||
#define VC_ENABLE (1 << 0)
|
||||
#define EXPORT_SRC_C (1 << 1)
|
||||
#define CS_PRIO(x) ((x) << 18)
|
||||
#define LS_PRIO(x) ((x) << 20)
|
||||
#define HS_PRIO(x) ((x) << 22)
|
||||
#define PS_PRIO(x) ((x) << 24)
|
||||
#define VS_PRIO(x) ((x) << 26)
|
||||
#define GS_PRIO(x) ((x) << 28)
|
||||
#define ES_PRIO(x) ((x) << 30)
|
||||
#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
|
||||
#define NUM_PS_GPRS(x) ((x) << 0)
|
||||
#define NUM_VS_GPRS(x) ((x) << 16)
|
||||
#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
|
||||
#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
|
||||
#define NUM_GS_GPRS(x) ((x) << 0)
|
||||
#define NUM_ES_GPRS(x) ((x) << 16)
|
||||
#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
|
||||
#define NUM_HS_GPRS(x) ((x) << 0)
|
||||
#define NUM_LS_GPRS(x) ((x) << 16)
|
||||
#define SQ_THREAD_RESOURCE_MGMT 0x8C18
|
||||
#define NUM_PS_THREADS(x) ((x) << 0)
|
||||
#define NUM_VS_THREADS(x) ((x) << 8)
|
||||
#define NUM_GS_THREADS(x) ((x) << 16)
|
||||
#define NUM_ES_THREADS(x) ((x) << 24)
|
||||
#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
|
||||
#define NUM_HS_THREADS(x) ((x) << 0)
|
||||
#define NUM_LS_THREADS(x) ((x) << 8)
|
||||
#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
|
||||
#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
|
||||
#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
|
||||
#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
|
||||
#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
|
||||
#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
|
||||
#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
|
||||
#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
|
||||
#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
|
||||
#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
|
||||
#define SQ_LDS_RESOURCE_MGMT 0x8E2C
|
||||
|
||||
#define SQ_MS_FIFO_SIZES 0x8CF0
|
||||
#define CACHE_FIFO_SIZE(x) ((x) << 0)
|
||||
#define FETCH_FIFO_HIWATER(x) ((x) << 8)
|
||||
#define DONE_FIFO_HIWATER(x) ((x) << 16)
|
||||
#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
|
||||
|
||||
#define SX_DEBUG_1 0x9058
|
||||
#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
|
||||
#define SX_EXPORT_BUFFER_SIZES 0x900C
|
||||
#define COLOR_BUFFER_SIZE(x) ((x) << 0)
|
||||
#define POSITION_BUFFER_SIZE(x) ((x) << 8)
|
||||
#define SMX_BUFFER_SIZE(x) ((x) << 16)
|
||||
#define SX_MISC 0x28350
|
||||
|
||||
#define CB_PERF_CTR0_SEL_0 0x9A20
|
||||
#define CB_PERF_CTR0_SEL_1 0x9A24
|
||||
#define CB_PERF_CTR1_SEL_0 0x9A28
|
||||
#define CB_PERF_CTR1_SEL_1 0x9A2C
|
||||
#define CB_PERF_CTR2_SEL_0 0x9A30
|
||||
#define CB_PERF_CTR2_SEL_1 0x9A34
|
||||
#define CB_PERF_CTR3_SEL_0 0x9A38
|
||||
#define CB_PERF_CTR3_SEL_1 0x9A3C
|
||||
|
||||
#define TA_CNTL_AUX 0x9508
|
||||
#define DISABLE_CUBE_WRAP (1 << 0)
|
||||
#define DISABLE_CUBE_ANISO (1 << 1)
|
||||
#define SYNC_GRADIENT (1 << 24)
|
||||
#define SYNC_WALKER (1 << 25)
|
||||
#define SYNC_ALIGNER (1 << 26)
|
||||
|
||||
#define VGT_CACHE_INVALIDATION 0x88C4
|
||||
#define CACHE_INVALIDATION(x) ((x) << 0)
|
||||
#define VC_ONLY 0
|
||||
#define TC_ONLY 1
|
||||
#define VC_AND_TC 2
|
||||
#define AUTO_INVLD_EN(x) ((x) << 6)
|
||||
#define NO_AUTO 0
|
||||
#define ES_AUTO 1
|
||||
#define GS_AUTO 2
|
||||
#define ES_AND_GS_AUTO 3
|
||||
#define VGT_GS_VERTEX_REUSE 0x88D4
|
||||
#define VGT_NUM_INSTANCES 0x8974
|
||||
#define VGT_OUT_DEALLOC_CNTL 0x28C5C
|
||||
#define DEALLOC_DIST_MASK 0x0000007F
|
||||
#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
|
||||
#define VTX_REUSE_DEPTH_MASK 0x000000FF
|
||||
|
||||
#define VM_CONTEXT0_CNTL 0x1410
|
||||
#define ENABLE_CONTEXT (1 << 0)
|
||||
#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
|
||||
#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
|
||||
#define VM_CONTEXT1_CNTL 0x1414
|
||||
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
|
||||
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
|
||||
#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
|
||||
#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
|
||||
#define RESPONSE_TYPE_MASK 0x000000F0
|
||||
#define RESPONSE_TYPE_SHIFT 4
|
||||
#define VM_L2_CNTL 0x1400
|
||||
#define ENABLE_L2_CACHE (1 << 0)
|
||||
#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
|
||||
#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
|
||||
#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
|
||||
#define VM_L2_CNTL2 0x1404
|
||||
#define INVALIDATE_ALL_L1_TLBS (1 << 0)
|
||||
#define INVALIDATE_L2_CACHE (1 << 1)
|
||||
#define VM_L2_CNTL3 0x1408
|
||||
#define BANK_SELECT(x) ((x) << 0)
|
||||
#define CACHE_UPDATE_MODE(x) ((x) << 6)
|
||||
#define VM_L2_STATUS 0x140C
|
||||
#define L2_BUSY (1 << 0)
|
||||
|
||||
#define WAIT_UNTIL 0x8040
|
||||
|
||||
#define SRBM_STATUS 0x0E50
|
||||
#define SRBM_SOFT_RESET 0x0E60
|
||||
#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
|
||||
#define SOFT_RESET_BIF (1 << 1)
|
||||
#define SOFT_RESET_CG (1 << 2)
|
||||
#define SOFT_RESET_DC (1 << 5)
|
||||
#define SOFT_RESET_GRBM (1 << 8)
|
||||
#define SOFT_RESET_HDP (1 << 9)
|
||||
#define SOFT_RESET_IH (1 << 10)
|
||||
#define SOFT_RESET_MC (1 << 11)
|
||||
#define SOFT_RESET_RLC (1 << 13)
|
||||
#define SOFT_RESET_ROM (1 << 14)
|
||||
#define SOFT_RESET_SEM (1 << 15)
|
||||
#define SOFT_RESET_VMC (1 << 17)
|
||||
#define SOFT_RESET_TST (1 << 21)
|
||||
#define SOFT_RESET_REGBB (1 << 22)
|
||||
#define SOFT_RESET_ORB (1 << 23)
|
||||
|
||||
#define IH_RB_CNTL 0x3e00
|
||||
# define IH_RB_ENABLE (1 << 0)
|
||||
# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
|
||||
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
|
||||
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
|
||||
# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
|
||||
# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
|
||||
#define IH_RB_BASE 0x3e04
|
||||
#define IH_RB_RPTR 0x3e08
|
||||
#define IH_RB_WPTR 0x3e0c
|
||||
# define RB_OVERFLOW (1 << 0)
|
||||
# define WPTR_OFFSET_MASK 0x3fffc
|
||||
#define IH_RB_WPTR_ADDR_HI 0x3e10
|
||||
#define IH_RB_WPTR_ADDR_LO 0x3e14
|
||||
#define IH_CNTL 0x3e18
|
||||
# define ENABLE_INTR (1 << 0)
|
||||
# define IH_MC_SWAP(x) ((x) << 2)
|
||||
# define IH_MC_SWAP_NONE 0
|
||||
# define IH_MC_SWAP_16BIT 1
|
||||
# define IH_MC_SWAP_32BIT 2
|
||||
# define IH_MC_SWAP_64BIT 3
|
||||
# define RPTR_REARM (1 << 4)
|
||||
# define MC_WRREQ_CREDIT(x) ((x) << 15)
|
||||
# define MC_WR_CLEAN_CNT(x) ((x) << 20)
|
||||
|
||||
#define CP_INT_CNTL 0xc124
|
||||
# define CNTX_BUSY_INT_ENABLE (1 << 19)
|
||||
# define CNTX_EMPTY_INT_ENABLE (1 << 20)
|
||||
# define SCRATCH_INT_ENABLE (1 << 25)
|
||||
# define TIME_STAMP_INT_ENABLE (1 << 26)
|
||||
# define IB2_INT_ENABLE (1 << 29)
|
||||
# define IB1_INT_ENABLE (1 << 30)
|
||||
# define RB_INT_ENABLE (1 << 31)
|
||||
#define CP_INT_STATUS 0xc128
|
||||
# define SCRATCH_INT_STAT (1 << 25)
|
||||
# define TIME_STAMP_INT_STAT (1 << 26)
|
||||
# define IB2_INT_STAT (1 << 29)
|
||||
# define IB1_INT_STAT (1 << 30)
|
||||
# define RB_INT_STAT (1 << 31)
|
||||
|
||||
#define GRBM_INT_CNTL 0x8060
|
||||
# define RDERR_INT_ENABLE (1 << 0)
|
||||
# define GUI_IDLE_INT_ENABLE (1 << 19)
|
||||
|
||||
/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
|
||||
#define CRTC_STATUS_FRAME_COUNT 0x6e98
|
||||
|
||||
/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
|
||||
#define VLINE_STATUS 0x6bb8
|
||||
# define VLINE_OCCURRED (1 << 0)
|
||||
# define VLINE_ACK (1 << 4)
|
||||
# define VLINE_STAT (1 << 12)
|
||||
# define VLINE_INTERRUPT (1 << 16)
|
||||
# define VLINE_INTERRUPT_TYPE (1 << 17)
|
||||
/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
|
||||
#define VBLANK_STATUS 0x6bbc
|
||||
# define VBLANK_OCCURRED (1 << 0)
|
||||
# define VBLANK_ACK (1 << 4)
|
||||
# define VBLANK_STAT (1 << 12)
|
||||
# define VBLANK_INTERRUPT (1 << 16)
|
||||
# define VBLANK_INTERRUPT_TYPE (1 << 17)
|
||||
|
||||
/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
|
||||
#define INT_MASK 0x6b40
|
||||
# define VBLANK_INT_MASK (1 << 0)
|
||||
# define VLINE_INT_MASK (1 << 4)
|
||||
|
||||
#define DISP_INTERRUPT_STATUS 0x60f4
|
||||
# define LB_D1_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D1_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD1_INTERRUPT (1 << 17)
|
||||
# define DC_HPD1_RX_INTERRUPT (1 << 18)
|
||||
# define DACA_AUTODETECT_INTERRUPT (1 << 22)
|
||||
# define DACB_AUTODETECT_INTERRUPT (1 << 23)
|
||||
# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
|
||||
# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
|
||||
# define LB_D2_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D2_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD2_INTERRUPT (1 << 17)
|
||||
# define DC_HPD2_RX_INTERRUPT (1 << 18)
|
||||
# define DISP_TIMER_INTERRUPT (1 << 24)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
|
||||
# define LB_D3_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D3_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD3_INTERRUPT (1 << 17)
|
||||
# define DC_HPD3_RX_INTERRUPT (1 << 18)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
|
||||
# define LB_D4_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D4_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD4_INTERRUPT (1 << 17)
|
||||
# define DC_HPD4_RX_INTERRUPT (1 << 18)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
|
||||
# define LB_D5_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D5_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD5_INTERRUPT (1 << 17)
|
||||
# define DC_HPD5_RX_INTERRUPT (1 << 18)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050
|
||||
# define LB_D6_VLINE_INTERRUPT (1 << 2)
|
||||
# define LB_D6_VBLANK_INTERRUPT (1 << 3)
|
||||
# define DC_HPD6_INTERRUPT (1 << 17)
|
||||
# define DC_HPD6_RX_INTERRUPT (1 << 18)
|
||||
|
||||
/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
|
||||
#define GRPH_INT_STATUS 0x6858
|
||||
# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
|
||||
# define GRPH_PFLIP_INT_CLEAR (1 << 8)
|
||||
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
|
||||
#define GRPH_INT_CONTROL 0x685c
|
||||
# define GRPH_PFLIP_INT_MASK (1 << 0)
|
||||
# define GRPH_PFLIP_INT_TYPE (1 << 8)
|
||||
|
||||
#define DACA_AUTODETECT_INT_CONTROL 0x66c8
|
||||
#define DACB_AUTODETECT_INT_CONTROL 0x67c8
|
||||
|
||||
#define DC_HPD1_INT_STATUS 0x601c
|
||||
#define DC_HPD2_INT_STATUS 0x6028
|
||||
#define DC_HPD3_INT_STATUS 0x6034
|
||||
#define DC_HPD4_INT_STATUS 0x6040
|
||||
#define DC_HPD5_INT_STATUS 0x604c
|
||||
#define DC_HPD6_INT_STATUS 0x6058
|
||||
# define DC_HPDx_INT_STATUS (1 << 0)
|
||||
# define DC_HPDx_SENSE (1 << 1)
|
||||
# define DC_HPDx_RX_INT_STATUS (1 << 8)
|
||||
|
||||
#define DC_HPD1_INT_CONTROL 0x6020
|
||||
#define DC_HPD2_INT_CONTROL 0x602c
|
||||
#define DC_HPD3_INT_CONTROL 0x6038
|
||||
#define DC_HPD4_INT_CONTROL 0x6044
|
||||
#define DC_HPD5_INT_CONTROL 0x6050
|
||||
#define DC_HPD6_INT_CONTROL 0x605c
|
||||
# define DC_HPDx_INT_ACK (1 << 0)
|
||||
# define DC_HPDx_INT_POLARITY (1 << 8)
|
||||
# define DC_HPDx_INT_EN (1 << 16)
|
||||
# define DC_HPDx_RX_INT_ACK (1 << 20)
|
||||
# define DC_HPDx_RX_INT_EN (1 << 24)
|
||||
|
||||
#define DC_HPD1_CONTROL 0x6024
|
||||
#define DC_HPD2_CONTROL 0x6030
|
||||
#define DC_HPD3_CONTROL 0x603c
|
||||
#define DC_HPD4_CONTROL 0x6048
|
||||
#define DC_HPD5_CONTROL 0x6054
|
||||
#define DC_HPD6_CONTROL 0x6060
|
||||
# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
|
||||
# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
|
||||
# define DC_HPDx_EN (1 << 28)
|
||||
|
||||
#endif
|
||||
|
|
@ -44,6 +44,9 @@
|
|||
#define R700_PFP_UCODE_SIZE 848
|
||||
#define R700_PM4_UCODE_SIZE 1360
|
||||
#define R700_RLC_UCODE_SIZE 1024
|
||||
#define EVERGREEN_PFP_UCODE_SIZE 1120
|
||||
#define EVERGREEN_PM4_UCODE_SIZE 1376
|
||||
#define EVERGREEN_RLC_UCODE_SIZE 768
|
||||
|
||||
/* Firmware Names */
|
||||
MODULE_FIRMWARE("radeon/R600_pfp.bin");
|
||||
|
|
@ -68,6 +71,18 @@ MODULE_FIRMWARE("radeon/RV710_pfp.bin");
|
|||
MODULE_FIRMWARE("radeon/RV710_me.bin");
|
||||
MODULE_FIRMWARE("radeon/R600_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/R700_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/CEDAR_me.bin");
|
||||
MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
|
||||
MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
|
||||
MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
|
||||
MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
|
||||
|
||||
int r600_debugfs_mc_info_init(struct radeon_device *rdev);
|
||||
|
||||
|
|
@ -75,6 +90,7 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev);
|
|||
int r600_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
void r600_gpu_init(struct radeon_device *rdev);
|
||||
void r600_fini(struct radeon_device *rdev);
|
||||
void r600_irq_disable(struct radeon_device *rdev);
|
||||
|
||||
/* hpd for digital panel detect/disconnect */
|
||||
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
|
||||
|
|
@ -1450,10 +1466,31 @@ int r600_init_microcode(struct radeon_device *rdev)
|
|||
chip_name = "RV710";
|
||||
rlc_chip_name = "R700";
|
||||
break;
|
||||
case CHIP_CEDAR:
|
||||
chip_name = "CEDAR";
|
||||
rlc_chip_name = "CEDAR";
|
||||
break;
|
||||
case CHIP_REDWOOD:
|
||||
chip_name = "REDWOOD";
|
||||
rlc_chip_name = "REDWOOD";
|
||||
break;
|
||||
case CHIP_JUNIPER:
|
||||
chip_name = "JUNIPER";
|
||||
rlc_chip_name = "JUNIPER";
|
||||
break;
|
||||
case CHIP_CYPRESS:
|
||||
case CHIP_HEMLOCK:
|
||||
chip_name = "CYPRESS";
|
||||
rlc_chip_name = "CYPRESS";
|
||||
break;
|
||||
default: BUG();
|
||||
}
|
||||
|
||||
if (rdev->family >= CHIP_RV770) {
|
||||
if (rdev->family >= CHIP_CEDAR) {
|
||||
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
|
||||
me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
|
||||
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
|
||||
} else if (rdev->family >= CHIP_RV770) {
|
||||
pfp_req_size = R700_PFP_UCODE_SIZE * 4;
|
||||
me_req_size = R700_PM4_UCODE_SIZE * 4;
|
||||
rlc_req_size = R700_RLC_UCODE_SIZE * 4;
|
||||
|
|
@ -1567,12 +1604,15 @@ int r600_cp_start(struct radeon_device *rdev)
|
|||
}
|
||||
radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
|
||||
radeon_ring_write(rdev, 0x1);
|
||||
if (rdev->family < CHIP_RV770) {
|
||||
radeon_ring_write(rdev, 0x3);
|
||||
radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
|
||||
} else {
|
||||
if (rdev->family >= CHIP_CEDAR) {
|
||||
radeon_ring_write(rdev, 0x0);
|
||||
radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
|
||||
} else if (rdev->family >= CHIP_RV770) {
|
||||
radeon_ring_write(rdev, 0x0);
|
||||
radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
|
||||
} else {
|
||||
radeon_ring_write(rdev, 0x3);
|
||||
radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
|
||||
}
|
||||
radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
|
||||
radeon_ring_write(rdev, 0);
|
||||
|
|
@ -2273,10 +2313,11 @@ static void r600_ih_ring_fini(struct radeon_device *rdev)
|
|||
}
|
||||
}
|
||||
|
||||
static void r600_rlc_stop(struct radeon_device *rdev)
|
||||
void r600_rlc_stop(struct radeon_device *rdev)
|
||||
{
|
||||
|
||||
if (rdev->family >= CHIP_RV770) {
|
||||
if ((rdev->family >= CHIP_RV770) &&
|
||||
(rdev->family <= CHIP_RV740)) {
|
||||
/* r7xx asics need to soft reset RLC before halting */
|
||||
WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
|
||||
RREG32(SRBM_SOFT_RESET);
|
||||
|
|
@ -2313,7 +2354,12 @@ static int r600_rlc_init(struct radeon_device *rdev)
|
|||
WREG32(RLC_UCODE_CNTL, 0);
|
||||
|
||||
fw_data = (const __be32 *)rdev->rlc_fw->data;
|
||||
if (rdev->family >= CHIP_RV770) {
|
||||
if (rdev->family >= CHIP_CEDAR) {
|
||||
for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
|
||||
WREG32(RLC_UCODE_ADDR, i);
|
||||
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
|
||||
}
|
||||
} else if (rdev->family >= CHIP_RV770) {
|
||||
for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
|
||||
WREG32(RLC_UCODE_ADDR, i);
|
||||
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
|
||||
|
|
@ -2343,7 +2389,7 @@ static void r600_enable_interrupts(struct radeon_device *rdev)
|
|||
rdev->ih.enabled = true;
|
||||
}
|
||||
|
||||
static void r600_disable_interrupts(struct radeon_device *rdev)
|
||||
void r600_disable_interrupts(struct radeon_device *rdev)
|
||||
{
|
||||
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
|
||||
u32 ih_cntl = RREG32(IH_CNTL);
|
||||
|
|
@ -2458,7 +2504,10 @@ int r600_irq_init(struct radeon_device *rdev)
|
|||
WREG32(IH_CNTL, ih_cntl);
|
||||
|
||||
/* force the active interrupt state to all disabled */
|
||||
r600_disable_interrupt_state(rdev);
|
||||
if (rdev->family >= CHIP_CEDAR)
|
||||
evergreen_disable_interrupt_state(rdev);
|
||||
else
|
||||
r600_disable_interrupt_state(rdev);
|
||||
|
||||
/* enable irqs */
|
||||
r600_enable_interrupts(rdev);
|
||||
|
|
@ -2468,7 +2517,7 @@ int r600_irq_init(struct radeon_device *rdev)
|
|||
|
||||
void r600_irq_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
r600_disable_interrupts(rdev);
|
||||
r600_irq_disable(rdev);
|
||||
r600_rlc_stop(rdev);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -372,7 +372,7 @@ struct radeon_irq {
|
|||
bool installed;
|
||||
bool sw_int;
|
||||
/* FIXME: use a define max crtc rather than hardcode it */
|
||||
bool crtc_vblank_int[2];
|
||||
bool crtc_vblank_int[6];
|
||||
wait_queue_head_t vblank_queue;
|
||||
/* FIXME: use defines for max hpd/dacs */
|
||||
bool hpd[6];
|
||||
|
|
@ -870,11 +870,36 @@ struct rv770_asic {
|
|||
struct r100_gpu_lockup lockup;
|
||||
};
|
||||
|
||||
struct evergreen_asic {
|
||||
unsigned num_ses;
|
||||
unsigned max_pipes;
|
||||
unsigned max_tile_pipes;
|
||||
unsigned max_simds;
|
||||
unsigned max_backends;
|
||||
unsigned max_gprs;
|
||||
unsigned max_threads;
|
||||
unsigned max_stack_entries;
|
||||
unsigned max_hw_contexts;
|
||||
unsigned max_gs_threads;
|
||||
unsigned sx_max_export_size;
|
||||
unsigned sx_max_export_pos_size;
|
||||
unsigned sx_max_export_smx_size;
|
||||
unsigned sq_num_cf_insts;
|
||||
unsigned sx_num_of_sets;
|
||||
unsigned sc_prim_fifo_size;
|
||||
unsigned sc_hiz_tile_fifo_size;
|
||||
unsigned sc_earlyz_tile_fifo_size;
|
||||
unsigned tiling_nbanks;
|
||||
unsigned tiling_npipes;
|
||||
unsigned tiling_group_size;
|
||||
};
|
||||
|
||||
union radeon_asic_config {
|
||||
struct r300_asic r300;
|
||||
struct r100_asic r100;
|
||||
struct r600_asic r600;
|
||||
struct rv770_asic rv770;
|
||||
struct evergreen_asic evergreen;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1272,6 +1297,7 @@ extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
|
|||
extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
|
||||
extern bool r600_card_posted(struct radeon_device *rdev);
|
||||
extern void r600_cp_stop(struct radeon_device *rdev);
|
||||
extern int r600_cp_start(struct radeon_device *rdev);
|
||||
extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
|
||||
extern int r600_cp_resume(struct radeon_device *rdev);
|
||||
extern void r600_cp_fini(struct radeon_device *rdev);
|
||||
|
|
@ -1295,6 +1321,8 @@ extern void r600_irq_fini(struct radeon_device *rdev);
|
|||
extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
|
||||
extern int r600_irq_set(struct radeon_device *rdev);
|
||||
extern void r600_irq_suspend(struct radeon_device *rdev);
|
||||
extern void r600_disable_interrupts(struct radeon_device *rdev);
|
||||
extern void r600_rlc_stop(struct radeon_device *rdev);
|
||||
/* r600 audio */
|
||||
extern int r600_audio_init(struct radeon_device *rdev);
|
||||
extern int r600_audio_tmds_index(struct drm_encoder *encoder);
|
||||
|
|
@ -1312,6 +1340,11 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
|
|||
uint8_t status_bits,
|
||||
uint8_t category_code);
|
||||
|
||||
extern void r700_cp_stop(struct radeon_device *rdev);
|
||||
extern void r700_cp_fini(struct radeon_device *rdev);
|
||||
extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
|
||||
extern int evergreen_irq_set(struct radeon_device *rdev);
|
||||
|
||||
/* evergreen */
|
||||
struct evergreen_mc_save {
|
||||
u32 vga_control[6];
|
||||
|
|
|
|||
|
|
@ -635,17 +635,17 @@ static struct radeon_asic evergreen_asic = {
|
|||
.fini = &evergreen_fini,
|
||||
.suspend = &evergreen_suspend,
|
||||
.resume = &evergreen_resume,
|
||||
.cp_commit = NULL,
|
||||
.cp_commit = &r600_cp_commit,
|
||||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
|
||||
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = NULL,
|
||||
.ring_ib_execute = NULL,
|
||||
.irq_set = NULL,
|
||||
.irq_process = NULL,
|
||||
.get_vblank_counter = NULL,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &r600_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
.fence_ring_emit = NULL,
|
||||
.cs_parse = NULL,
|
||||
.copy_blit = NULL,
|
||||
|
|
|
|||
|
|
@ -281,6 +281,7 @@ int rv770_resume(struct radeon_device *rdev);
|
|||
/*
|
||||
* evergreen
|
||||
*/
|
||||
void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
int evergreen_init(struct radeon_device *rdev);
|
||||
void evergreen_fini(struct radeon_device *rdev);
|
||||
int evergreen_suspend(struct radeon_device *rdev);
|
||||
|
|
@ -293,4 +294,8 @@ void evergreen_hpd_fini(struct radeon_device *rdev);
|
|||
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
|
||||
void evergreen_hpd_set_polarity(struct radeon_device *rdev,
|
||||
enum radeon_hpd_id hpd);
|
||||
u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
|
||||
int evergreen_irq_set(struct radeon_device *rdev);
|
||||
int evergreen_irq_process(struct radeon_device *rdev);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1462,6 +1462,10 @@ static const char *pp_lib_thermal_controller_names[] = {
|
|||
"RV6xx",
|
||||
"RV770",
|
||||
"ADT7473",
|
||||
"External GPIO",
|
||||
"Evergreen",
|
||||
"ADT7473 with internal",
|
||||
|
||||
};
|
||||
|
||||
union power_info {
|
||||
|
|
@ -1707,15 +1711,21 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
}
|
||||
} else if (frev == 4) {
|
||||
} else {
|
||||
/* add the i2c bus for thermal/fan chip */
|
||||
/* no support for internal controller yet */
|
||||
if (power_info->info_4.sThermalController.ucType > 0) {
|
||||
if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
|
||||
(power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
|
||||
(power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
|
||||
(power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
|
||||
DRM_INFO("Internal thermal controller %s fan control\n",
|
||||
(power_info->info_4.sThermalController.ucFanParameters &
|
||||
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
|
||||
} else if ((power_info->info_4.sThermalController.ucType ==
|
||||
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
|
||||
(power_info->info_4.sThermalController.ucType ==
|
||||
ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
|
||||
DRM_INFO("Special thermal controller config\n");
|
||||
} else {
|
||||
DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
|
||||
pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
|
||||
|
|
@ -1763,6 +1773,36 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
|
|||
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
|
||||
clock_info->usVDDC;
|
||||
mode_index++;
|
||||
} else if (ASIC_IS_DCE4(rdev)) {
|
||||
struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
|
||||
(struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
|
||||
(mode_info->atom_context->bios +
|
||||
data_offset +
|
||||
le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
|
||||
(power_state->ucClockStateIndices[j] *
|
||||
power_info->info_4.ucClockInfoSize));
|
||||
sclk = le16_to_cpu(clock_info->usEngineClockLow);
|
||||
sclk |= clock_info->ucEngineClockHigh << 16;
|
||||
mclk = le16_to_cpu(clock_info->usMemoryClockLow);
|
||||
mclk |= clock_info->ucMemoryClockHigh << 16;
|
||||
rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
|
||||
rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
|
||||
/* skip invalid modes */
|
||||
if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
|
||||
(rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
|
||||
continue;
|
||||
/* skip overclock modes for now */
|
||||
if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
|
||||
rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
|
||||
(rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
|
||||
rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
|
||||
continue;
|
||||
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
|
||||
VOLTAGE_SW;
|
||||
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
|
||||
clock_info->usVDDC;
|
||||
/* XXX usVDDCI */
|
||||
mode_index++;
|
||||
} else {
|
||||
struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
|
||||
(struct _ATOM_PPLIB_R600_CLOCK_INFO *)
|
||||
|
|
|
|||
|
|
@ -237,7 +237,6 @@ void r700_cp_stop(struct radeon_device *rdev)
|
|||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
||||
}
|
||||
|
||||
|
||||
static int rv770_cp_load_microcode(struct radeon_device *rdev)
|
||||
{
|
||||
const __be32 *fw_data;
|
||||
|
|
@ -272,6 +271,11 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void r700_cp_fini(struct radeon_device *rdev)
|
||||
{
|
||||
r700_cp_stop(rdev);
|
||||
radeon_ring_fini(rdev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Core functions
|
||||
|
|
@ -1126,7 +1130,7 @@ int rv770_init(struct radeon_device *rdev)
|
|||
r = rv770_startup(rdev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
||||
r600_cp_fini(rdev);
|
||||
r700_cp_fini(rdev);
|
||||
r600_wb_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_irq_kms_fini(rdev);
|
||||
|
|
@ -1160,7 +1164,7 @@ void rv770_fini(struct radeon_device *rdev)
|
|||
{
|
||||
radeon_pm_fini(rdev);
|
||||
r600_blit_fini(rdev);
|
||||
r600_cp_fini(rdev);
|
||||
r700_cp_fini(rdev);
|
||||
r600_wb_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_irq_kms_fini(rdev);
|
||||
|
|
|
|||
Loading…
Reference in a new issue