drm/radeon: fix up audio dto programming for DCE2
Uses a different register than DCE3 asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -246,9 +246,18 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
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WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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if (ASIC_IS_DCE3(rdev)) {
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/* according to the reg specs, this should DCE3.2 only, but in
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* practice it seems to cover DCE3.0 as well.
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*/
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WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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} else {
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/* according to the reg specs, this should be DCE2.0 and DCE3.0 */
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WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |
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AUDIO_DTO_MODULE(clock * 100));
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}
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}
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/*
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@ -910,7 +910,12 @@
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# define TARGET_LINK_SPEED_MASK (0xf << 0)
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# define SELECTABLE_DEEMPHASIS (1 << 6)
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/* Audio clocks */
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/* Audio clocks DCE 2.0/3.0 */
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#define AUDIO_DTO 0x7340
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# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
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# define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16)
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/* Audio clocks DCE 3.2 */
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#define DCCG_AUDIO_DTO0_PHASE 0x0514
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#define DCCG_AUDIO_DTO0_MODULE 0x0518
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#define DCCG_AUDIO_DTO0_LOAD 0x051c
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