redonkable/alistair23-linux
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Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-next

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A few more DPM fixes.

* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
  drm/radeon/tn: disable PG when changing UVD clocks
  drm/radeon/sumo: disable PG when changing UVD clocks
  drm/radeon/aruba: disable additional rlc features
  drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()
  drm/radeon/dpm: fix compilation with certain versions of gcc
  drm/radeon/dpm: clarify debugfs warning
This commit is contained in:
Dave Airlie 2013-07-04 10:44:06 +10:00
parent e5ad449be6 338a95a955
commit 1586ba727f
9 changed files with 37 additions and 6 deletions
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2
drivers/gpu/drm/radeon/evergreen.c
View file

@ -4043,8 +4043,6 @@ static void evergreen_rlc_start(struct radeon_device *rdev)
if (rdev->flags & RADEON_IS_IGP) {
mask |= GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC;
if (rdev->family == CHIP_ARUBA)
mask |= DYN_PER_SIMD_PG_ENABLE | LB_CNT_SPIM_ACTIVE | LOAD_BALANCE_ENABLE;
}
WREG32(RLC_CNTL, mask);

1
drivers/gpu/drm/radeon/ni_dpm.c
View file

@ -28,6 +28,7 @@
#include "ni_dpm.h"
#include "atom.h"
#include <linux/math64.h>
#include <linux/seq_file.h>
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b

2
drivers/gpu/drm/radeon/radeon_atombios.c
View file

@ -3639,7 +3639,7 @@ int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
p = (u8 *)vram_module->asMemTiming;
for (i = 0; i < mclk_range_table->num_entries; i++) {
format = (ATOM_MEMORY_TIMING_FORMAT *)p;
mclk_range_table->mclk[i] = format->ulClkRange;
mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
p += mem_timing_size;
}
} else

2
drivers/gpu/drm/radeon/radeon_pm.c
View file

@ -1399,7 +1399,7 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
if (rdev->asic->dpm.debugfs_print_current_performance_level)
radeon_dpm_debugfs_print_current_performance_level(rdev, m);
else
seq_printf(m, "Unsupported\n");
seq_printf(m, "Debugfs support not implemented for this asic\n");
mutex_unlock(&rdev->pm.mutex);
} else {
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);

1
drivers/gpu/drm/radeon/rv6xx_dpm.c
View file

@ -28,6 +28,7 @@
#include "r600_dpm.h"
#include "rv6xx_dpm.h"
#include "atom.h"
#include <linux/seq_file.h>
static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
u32 unscaled_count, u32 unit);

1
drivers/gpu/drm/radeon/rv770_dpm.c
View file

@ -29,6 +29,7 @@
#include "rv770_dpm.h"
#include "cypress_dpm.h"
#include "atom.h"
#include <linux/seq_file.h>
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b

1
drivers/gpu/drm/radeon/si_dpm.c
View file

@ -28,6 +28,7 @@
#include "si_dpm.h"
#include "atom.h"
#include <linux/math64.h>
#include <linux/seq_file.h>
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b

24
drivers/gpu/drm/radeon/sumo_dpm.c
View file

@ -27,6 +27,7 @@
#include "r600_dpm.h"
#include "cypress_dpm.h"
#include "sumo_dpm.h"
#include <linux/seq_file.h>
#define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
#define SUMO_MINIMUM_ENGINE_CLOCK 800
@ -810,6 +811,25 @@ static void sumo_program_bootup_state(struct radeon_device *rdev)
sumo_power_level_enable(rdev, i, false);
}
static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
struct radeon_ps *new_rps,
struct radeon_ps *old_rps)
{
struct sumo_power_info *pi = sumo_get_pi(rdev);
if (pi->enable_gfx_power_gating) {
sumo_gfx_powergating_enable(rdev, false);
}
radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
if (pi->enable_gfx_power_gating) {
if (!pi->disable_gfx_power_gating_in_uvd ||
!r600_is_uvd_state(new_rps->class, new_rps->class2))
sumo_gfx_powergating_enable(rdev, true);
}
}
static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
struct radeon_ps *new_rps,
struct radeon_ps *old_rps)
@ -825,7 +845,7 @@ static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
current_ps->levels[current_ps->num_levels - 1].sclk)
return;
radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
}
static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
@ -843,7 +863,7 @@ static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
current_ps->levels[current_ps->num_levels - 1].sclk)
return;
radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
}
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)

9
drivers/gpu/drm/radeon/trinity_dpm.c
View file

@ -26,6 +26,7 @@
#include "trinityd.h"
#include "r600_dpm.h"
#include "trinity_dpm.h"
#include <linux/seq_file.h>
#define TRINITY_MAX_DEEPSLEEP_DIVIDER_ID 5
#define TRINITY_MINIMUM_ENGINE_CLOCK 800
@ -920,6 +921,10 @@ static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
{
struct trinity_power_info *pi = trinity_get_pi(rdev);
if (pi->enable_gfx_power_gating) {
trinity_gfx_powergating_enable(rdev, false);
}
if (pi->uvd_dpm) {
if (trinity_uvd_clocks_zero(new_rps) &&
!trinity_uvd_clocks_zero(old_rps)) {
@ -945,6 +950,10 @@ static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
}
if (pi->enable_gfx_power_gating) {
trinity_gfx_powergating_enable(rdev, true);
}
}
static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,