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clk: imx: add clocks for parallel capture interface of IMX8QXP 

Add clocks for parallel port capture interface of IMX8QXP.
Because digital pll for parallel interface is on by default, and
not provide enable/disable function by scu, so add the related ops
for this kind of clocks.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Guoniu.zhou 2019-04-24 17:51:12 +08:00 committed by Dong Aisheng
parent a1b58d4754
commit 15ea9f22fd
5 changed files with 50 additions and 3 deletions
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14
drivers/clk/imx/clk-imx8qxp-lpcg.c
View File

@ -280,6 +280,19 @@ static const struct imx8qxp_ss_lpcg imx8qxp_ss_csi1 = {
.num_max = IMX_CSI_LPCG_CSI1_CLK_END,
};
static const struct imx8qxp_lpcg_data imx8qxp_lpcg_pi[] = {
{ IMX_PI_LPCG_PI0_PIXEL_CLK, "pi_lpcg_pi0_pixel_clk", "pi_per_div_clk", 0, PI_PI0_PIXEL_LPCG, 0, 0, },
{ IMX_PI_LPCG_PI0_IPG_CLK, "pi_lpcg_pi0_ipg_clk", "pi_per_div_clk", 0, PI_PI0_IPG_LPCG, 16, 0, },
{ IMX_PI_LPCG_PI0_MISC_CLK, "pi_lpcg_pi0_misc_clk", "pi_mclk_div_clk", 0, PI_PI0_MISC_LPCG, 0, 0, },
};
static const struct imx8qxp_ss_lpcg imx8qxp_ss_pi = {
.lpcg = imx8qxp_lpcg_pi,
.num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_pi),
.num_max = IMX_PI_LPCG_CLK_END,
};
static const struct imx8qxp_lpcg_data imx8qxp_lpcg_dc[] = {
{ IMX_DC0_LPCG_PRG0_RTRAM_CLK, "dc0_lpcg_prg0_rtram_clk", "dc_axi_ext_clk_root", 0, 0x20, 0, 0, },
{ IMX_DC0_LPCG_PRG0_APB_CLK, "dc0_lpcg_prg0_apb_clk", "dc_cfg_clk_root", 0, 0x20, 16, 0, },
@ -413,6 +426,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
{ .compatible = "fsl,imx8qxp-lpcg-img", &imx8qxp_ss_img, },
{ .compatible = "fsl,imx8qxp-lpcg-csi0", &imx8qxp_ss_csi0, },
{ .compatible = "fsl,imx8qxp-lpcg-csi1", &imx8qxp_ss_csi1, },
{ .compatible = "fsl,imx8qxp-lpcg-pi", &imx8qxp_ss_pi, },
{ .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, },
{ .compatible = "fsl,imx8qxp-lpcg-mipi0", &imx8qxp_ss_mipi0, },
{ .compatible = "fsl,imx8qxp-lpcg-mipi1", &imx8qxp_ss_mipi1, },

5
drivers/clk/imx/clk-imx8qxp-lpcg.h
View File

@ -136,6 +136,11 @@
#define CSI_CSI1_ESC_LPCG 0x1C
#define CSI_CSI1_I2C0_LPCG 0x14
/* Parallel Interface SS */
#define PI_PI0_PIXEL_LPCG 0x18
#define PI_PI0_IPG_LPCG 0x04
#define PI_PI0_MISC_LPCG 0x1C
/* DC0 SS */
/* TODO: ADD DC LPCGs */

13
drivers/clk/imx/clk-imx8qxp.c
View File

@ -25,6 +25,14 @@ static const char *sdhc0_sels[] = {
"dummy",
};
static const char *pll0_sels[] = {
"dummy",
"pi_dpll_clk",
"dummy",
"dummy",
"dummy",
};
static int imx8qxp_clk_probe(struct platform_device *pdev)
{
struct device_node *ccm_node = pdev->dev.of_node;
@ -173,6 +181,11 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_CSI1_I2C0_CLK] = imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER);
clks[IMX_CSI1_PWM0_CLK] = imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER);
/* Parallel Interface SS */
clks[IMX_PARALLEL_DPLL_CLK] = imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL);
clks[IMX_PARALLEL_PER_DIV_CLK] = imx_clk_scu2("pi_per_div_clk", pll0_sels, ARRAY_SIZE(pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER);
clks[IMX_PARALLEL_MCLK_DIV_CLK] = imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0);
/* GPU SS */
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);

8
drivers/clk/imx/clk-scu.c
View File

@ -344,6 +344,12 @@ static const struct clk_ops clk_scu_cpu_ops = {
.unprepare = clk_scu_unprepare,
};
static const struct clk_ops clk_scu_pi_ops = {
.recalc_rate = clk_scu_recalc_rate,
.round_rate = clk_scu_round_rate,
.set_rate = clk_scu_set_rate,
};
struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
int num_parents, u32 rsrc_id, u8 clk_type)
{
@ -363,6 +369,8 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
init.ops = &clk_scu_ops;
if (rsrc_id == IMX_SC_R_A35)
init.ops = &clk_scu_cpu_ops;
else if (rsrc_id == IMX_SC_R_PI_0_PLL)
init.ops = &clk_scu_pi_ops;
else
init.ops = &clk_scu_ops;
init.parent_names = parents;

13
include/dt-bindings/clock/imx8-clock.h
View File

@ -113,9 +113,9 @@
#define IMX_CSI1_I2C0_CLK 137
/* PARALLER CSI SS */
#define IMX_PARALLEL_CSI_DPLL_CLK 140
#define IMX_PARALLEL_CSI_PIXEL_CLK 141
#define IMX_PARALLEL_CSI_MCLK_CLK 142
#define IMX_PARALLEL_DPLL_CLK 140
#define IMX_PARALLEL_PER_DIV_CLK 141
#define IMX_PARALLEL_MCLK_DIV_CLK 142
/* VPU SS */
#define IMX_VPU_ENC_CLK 150
@ -461,6 +461,13 @@
#define IMX_CSI_LPCG_CSI1_CLK_END 3
/* Parallel Interface SS LPCG */
#define IMX_PI_LPCG_PI0_PIXEL_CLK 0
#define IMX_PI_LPCG_PI0_IPG_CLK 1
#define IMX_PI_LPCG_PI0_MISC_CLK 2
#define IMX_PI_LPCG_CLK_END 3
/* DC SS LPCG */
#define IMX_DC0_LPCG_PRG0_RTRAM_CLK 0
#define IMX_DC0_LPCG_PRG0_APB_CLK 1