Merge branches 'acpi-processor', 'acpi-cppc' and 'acpi-pmic'
* acpi-processor: ACPI / Processor: Drop setup_max_cpus check from acpi_processor_add() * acpi-cppc: ACPI / CPPC: add sysfs entries for CPPC perf capabilities ACPI / CPPC: Read lowest nonlinear perf in cppc_get_perf_caps() * acpi-pmic: ACPI / PMIC: Stop xpower OPRegion handler relying on IIO ACPI / PMIC: Add opregion driver for Intel CHT Whiskey Cove PMIC
This commit is contained in:
commit
168f4a6950
|
@ -506,7 +506,7 @@ config CRC_PMIC_OPREGION
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|||
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config XPOWER_PMIC_OPREGION
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bool "ACPI operation region support for XPower AXP288 PMIC"
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depends on AXP288_ADC = y
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depends on MFD_AXP20X_I2C
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help
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This config adds ACPI operation region support for XPower AXP288 PMIC.
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@ -516,6 +516,12 @@ config BXT_WC_PMIC_OPREGION
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help
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This config adds ACPI operation region support for BXT WhiskeyCove PMIC.
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config CHT_WC_PMIC_OPREGION
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bool "ACPI operation region support for CHT Whiskey Cove PMIC"
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depends on INTEL_SOC_PMIC_CHTWC
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help
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This config adds ACPI operation region support for CHT Whiskey Cove PMIC.
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endif
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config ACPI_CONFIGFS
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@ -101,6 +101,7 @@ obj-$(CONFIG_PMIC_OPREGION) += pmic/intel_pmic.o
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obj-$(CONFIG_CRC_PMIC_OPREGION) += pmic/intel_pmic_crc.o
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obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
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obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
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obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
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obj-$(CONFIG_ACPI_CONFIGFS) += acpi_configfs.o
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@ -388,11 +388,6 @@ static int acpi_processor_add(struct acpi_device *device,
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if (result) /* Processor is not physically present or unavailable */
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return 0;
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#ifdef CONFIG_SMP
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if (pr->id >= setup_max_cpus && pr->id != 0)
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return 0;
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#endif
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BUG_ON(pr->id >= nr_cpu_ids);
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/*
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@ -132,49 +132,54 @@ __ATTR(_name, 0444, show_##_name, NULL)
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#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
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#define show_cppc_data(access_fn, struct_name, member_name) \
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static ssize_t show_##member_name(struct kobject *kobj, \
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struct attribute *attr, char *buf) \
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{ \
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struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
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struct struct_name st_name = {0}; \
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int ret; \
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\
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ret = access_fn(cpc_ptr->cpu_id, &st_name); \
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if (ret) \
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return ret; \
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\
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return scnprintf(buf, PAGE_SIZE, "%llu\n", \
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(u64)st_name.member_name); \
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} \
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define_one_cppc_ro(member_name)
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show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
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show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
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show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
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show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
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show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
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show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
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static ssize_t show_feedback_ctrs(struct kobject *kobj,
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struct attribute *attr, char *buf)
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{
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struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
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struct cppc_perf_fb_ctrs fb_ctrs = {0};
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int ret;
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cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
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ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
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if (ret)
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return ret;
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return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
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fb_ctrs.reference, fb_ctrs.delivered);
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}
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define_one_cppc_ro(feedback_ctrs);
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static ssize_t show_reference_perf(struct kobject *kobj,
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struct attribute *attr, char *buf)
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{
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struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
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struct cppc_perf_fb_ctrs fb_ctrs = {0};
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cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
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return scnprintf(buf, PAGE_SIZE, "%llu\n",
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fb_ctrs.reference_perf);
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}
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define_one_cppc_ro(reference_perf);
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static ssize_t show_wraparound_time(struct kobject *kobj,
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struct attribute *attr, char *buf)
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{
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struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
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struct cppc_perf_fb_ctrs fb_ctrs = {0};
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cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
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return scnprintf(buf, PAGE_SIZE, "%llu\n", fb_ctrs.ctr_wrap_time);
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}
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define_one_cppc_ro(wraparound_time);
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static struct attribute *cppc_attrs[] = {
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&feedback_ctrs.attr,
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&reference_perf.attr,
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&wraparound_time.attr,
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&highest_perf.attr,
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&lowest_perf.attr,
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&lowest_nonlinear_perf.attr,
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&nominal_perf.attr,
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NULL
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};
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@ -972,9 +977,9 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
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int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
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struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
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*nom_perf;
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u64 high, low, nom;
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struct cpc_register_resource *highest_reg, *lowest_reg,
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*lowest_non_linear_reg, *nominal_reg;
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u64 high, low, nom, min_nonlinear;
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int ret = 0, regs_in_pcc = 0;
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if (!cpc_desc) {
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@ -984,12 +989,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
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highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
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lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
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ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
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nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
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lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
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nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
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/* Are any of the regs PCC ?*/
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if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
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CPC_IN_PCC(ref_perf) || CPC_IN_PCC(nom_perf)) {
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CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg)) {
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regs_in_pcc = 1;
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down_write(&pcc_data.pcc_lock);
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/* Ring doorbell once to update PCC subspace */
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@ -1005,10 +1010,13 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
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cpc_read(cpunum, lowest_reg, &low);
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perf_caps->lowest_perf = low;
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cpc_read(cpunum, nom_perf, &nom);
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cpc_read(cpunum, nominal_reg, &nom);
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perf_caps->nominal_perf = nom;
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if (!high || !low || !nom)
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cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
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perf_caps->lowest_nonlinear_perf = min_nonlinear;
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if (!high || !low || !nom || !min_nonlinear)
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ret = -EFAULT;
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out_err:
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@ -1083,7 +1091,7 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
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perf_fb_ctrs->delivered = delivered;
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perf_fb_ctrs->reference = reference;
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perf_fb_ctrs->reference_perf = ref_perf;
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perf_fb_ctrs->ctr_wrap_time = ctr_wrap_time;
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perf_fb_ctrs->wraparound_time = ctr_wrap_time;
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out_err:
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if (regs_in_pcc)
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up_write(&pcc_data.pcc_lock);
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280
drivers/acpi/pmic/intel_pmic_chtwc.c
Normal file
280
drivers/acpi/pmic/intel_pmic_chtwc.c
Normal file
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@ -0,0 +1,280 @@
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/*
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* Intel CHT Whiskey Cove PMIC operation region driver
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "intel_pmic.h"
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#define CHT_WC_V1P05A_CTRL 0x6e3b
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#define CHT_WC_V1P15_CTRL 0x6e3c
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#define CHT_WC_V1P05A_VSEL 0x6e3d
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#define CHT_WC_V1P15_VSEL 0x6e3e
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#define CHT_WC_V1P8A_CTRL 0x6e56
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#define CHT_WC_V1P8SX_CTRL 0x6e57
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#define CHT_WC_VDDQ_CTRL 0x6e58
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#define CHT_WC_V1P2A_CTRL 0x6e59
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#define CHT_WC_V1P2SX_CTRL 0x6e5a
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#define CHT_WC_V1P8A_VSEL 0x6e5b
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#define CHT_WC_VDDQ_VSEL 0x6e5c
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#define CHT_WC_V2P8SX_CTRL 0x6e5d
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#define CHT_WC_V3P3A_CTRL 0x6e5e
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#define CHT_WC_V3P3SD_CTRL 0x6e5f
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#define CHT_WC_VSDIO_CTRL 0x6e67
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#define CHT_WC_V3P3A_VSEL 0x6e68
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#define CHT_WC_VPROG1A_CTRL 0x6e90
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#define CHT_WC_VPROG1B_CTRL 0x6e91
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#define CHT_WC_VPROG1F_CTRL 0x6e95
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#define CHT_WC_VPROG2D_CTRL 0x6e99
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#define CHT_WC_VPROG3A_CTRL 0x6e9a
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#define CHT_WC_VPROG3B_CTRL 0x6e9b
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#define CHT_WC_VPROG4A_CTRL 0x6e9c
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#define CHT_WC_VPROG4B_CTRL 0x6e9d
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#define CHT_WC_VPROG4C_CTRL 0x6e9e
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#define CHT_WC_VPROG4D_CTRL 0x6e9f
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#define CHT_WC_VPROG5A_CTRL 0x6ea0
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#define CHT_WC_VPROG5B_CTRL 0x6ea1
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#define CHT_WC_VPROG6A_CTRL 0x6ea2
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#define CHT_WC_VPROG6B_CTRL 0x6ea3
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#define CHT_WC_VPROG1A_VSEL 0x6ec0
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#define CHT_WC_VPROG1B_VSEL 0x6ec1
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#define CHT_WC_V1P8SX_VSEL 0x6ec2
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#define CHT_WC_V1P2SX_VSEL 0x6ec3
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#define CHT_WC_V1P2A_VSEL 0x6ec4
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#define CHT_WC_VPROG1F_VSEL 0x6ec5
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#define CHT_WC_VSDIO_VSEL 0x6ec6
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#define CHT_WC_V2P8SX_VSEL 0x6ec7
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#define CHT_WC_V3P3SD_VSEL 0x6ec8
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#define CHT_WC_VPROG2D_VSEL 0x6ec9
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#define CHT_WC_VPROG3A_VSEL 0x6eca
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#define CHT_WC_VPROG3B_VSEL 0x6ecb
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#define CHT_WC_VPROG4A_VSEL 0x6ecc
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#define CHT_WC_VPROG4B_VSEL 0x6ecd
|
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#define CHT_WC_VPROG4C_VSEL 0x6ece
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#define CHT_WC_VPROG4D_VSEL 0x6ecf
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#define CHT_WC_VPROG5A_VSEL 0x6ed0
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#define CHT_WC_VPROG5B_VSEL 0x6ed1
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#define CHT_WC_VPROG6A_VSEL 0x6ed2
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#define CHT_WC_VPROG6B_VSEL 0x6ed3
|
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|
||||
/*
|
||||
* Regulator support is based on the non upstream patch:
|
||||
* "regulator: whiskey_cove: implements Whiskey Cove pmic VRF support"
|
||||
* https://github.com/intel-aero/meta-intel-aero/blob/master/recipes-kernel/linux/linux-yocto/0019-regulator-whiskey_cove-implements-WhiskeyCove-pmic-V.patch
|
||||
*/
|
||||
static struct pmic_table power_table[] = {
|
||||
{
|
||||
.address = 0x0,
|
||||
.reg = CHT_WC_V1P8A_CTRL,
|
||||
.bit = 0x01,
|
||||
}, /* V18A */
|
||||
{
|
||||
.address = 0x04,
|
||||
.reg = CHT_WC_V1P8SX_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* V18X */
|
||||
{
|
||||
.address = 0x08,
|
||||
.reg = CHT_WC_VDDQ_CTRL,
|
||||
.bit = 0x01,
|
||||
}, /* VDDQ */
|
||||
{
|
||||
.address = 0x0c,
|
||||
.reg = CHT_WC_V1P2A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* V12A */
|
||||
{
|
||||
.address = 0x10,
|
||||
.reg = CHT_WC_V1P2SX_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* V12X */
|
||||
{
|
||||
.address = 0x14,
|
||||
.reg = CHT_WC_V2P8SX_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* V28X */
|
||||
{
|
||||
.address = 0x18,
|
||||
.reg = CHT_WC_V3P3A_CTRL,
|
||||
.bit = 0x01,
|
||||
}, /* V33A */
|
||||
{
|
||||
.address = 0x1c,
|
||||
.reg = CHT_WC_V3P3SD_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* V3SD */
|
||||
{
|
||||
.address = 0x20,
|
||||
.reg = CHT_WC_VSDIO_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VSD */
|
||||
/* {
|
||||
.address = 0x24,
|
||||
.reg = ??,
|
||||
.bit = ??,
|
||||
}, ** VSW2 */
|
||||
/* {
|
||||
.address = 0x28,
|
||||
.reg = ??,
|
||||
.bit = ??,
|
||||
}, ** VSW1 */
|
||||
/* {
|
||||
.address = 0x2c,
|
||||
.reg = ??,
|
||||
.bit = ??,
|
||||
}, ** VUPY */
|
||||
/* {
|
||||
.address = 0x30,
|
||||
.reg = ??,
|
||||
.bit = ??,
|
||||
}, ** VRSO */
|
||||
{
|
||||
.address = 0x34,
|
||||
.reg = CHT_WC_VPROG1A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP1A */
|
||||
{
|
||||
.address = 0x38,
|
||||
.reg = CHT_WC_VPROG1B_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP1B */
|
||||
{
|
||||
.address = 0x3c,
|
||||
.reg = CHT_WC_VPROG1F_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP1F */
|
||||
{
|
||||
.address = 0x40,
|
||||
.reg = CHT_WC_VPROG2D_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP2D */
|
||||
{
|
||||
.address = 0x44,
|
||||
.reg = CHT_WC_VPROG3A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP3A */
|
||||
{
|
||||
.address = 0x48,
|
||||
.reg = CHT_WC_VPROG3B_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP3B */
|
||||
{
|
||||
.address = 0x4c,
|
||||
.reg = CHT_WC_VPROG4A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP4A */
|
||||
{
|
||||
.address = 0x50,
|
||||
.reg = CHT_WC_VPROG4B_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP4B */
|
||||
{
|
||||
.address = 0x54,
|
||||
.reg = CHT_WC_VPROG4C_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP4C */
|
||||
{
|
||||
.address = 0x58,
|
||||
.reg = CHT_WC_VPROG4D_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP4D */
|
||||
{
|
||||
.address = 0x5c,
|
||||
.reg = CHT_WC_VPROG5A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP5A */
|
||||
{
|
||||
.address = 0x60,
|
||||
.reg = CHT_WC_VPROG5B_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP5B */
|
||||
{
|
||||
.address = 0x64,
|
||||
.reg = CHT_WC_VPROG6A_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP6A */
|
||||
{
|
||||
.address = 0x68,
|
||||
.reg = CHT_WC_VPROG6B_CTRL,
|
||||
.bit = 0x07,
|
||||
}, /* VP6B */
|
||||
/* {
|
||||
.address = 0x6c,
|
||||
.reg = ??,
|
||||
.bit = ??,
|
||||
} ** VP7A */
|
||||
};
|
||||
|
||||
static int intel_cht_wc_pmic_get_power(struct regmap *regmap, int reg,
|
||||
int bit, u64 *value)
|
||||
{
|
||||
int data;
|
||||
|
||||
if (regmap_read(regmap, reg, &data))
|
||||
return -EIO;
|
||||
|
||||
*value = (data & bit) ? 1 : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int intel_cht_wc_pmic_update_power(struct regmap *regmap, int reg,
|
||||
int bitmask, bool on)
|
||||
{
|
||||
return regmap_update_bits(regmap, reg, bitmask, on ? 1 : 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* The thermal table and ops are empty, we do not support the Thermal opregion
|
||||
* (DPTF) due to lacking documentation.
|
||||
*/
|
||||
static struct intel_pmic_opregion_data intel_cht_wc_pmic_opregion_data = {
|
||||
.get_power = intel_cht_wc_pmic_get_power,
|
||||
.update_power = intel_cht_wc_pmic_update_power,
|
||||
.power_table = power_table,
|
||||
.power_table_count = ARRAY_SIZE(power_table),
|
||||
};
|
||||
|
||||
static int intel_cht_wc_pmic_opregion_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
|
||||
|
||||
return intel_pmic_install_opregion_handler(&pdev->dev,
|
||||
ACPI_HANDLE(pdev->dev.parent),
|
||||
pmic->regmap,
|
||||
&intel_cht_wc_pmic_opregion_data);
|
||||
}
|
||||
|
||||
static struct platform_device_id cht_wc_opregion_id_table[] = {
|
||||
{ .name = "cht_wcove_region" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, cht_wc_opregion_id_table);
|
||||
|
||||
static struct platform_driver intel_cht_wc_pmic_opregion_driver = {
|
||||
.probe = intel_cht_wc_pmic_opregion_probe,
|
||||
.driver = {
|
||||
.name = "cht_whiskey_cove_pmic",
|
||||
},
|
||||
.id_table = cht_wc_opregion_id_table,
|
||||
};
|
||||
module_platform_driver(intel_cht_wc_pmic_opregion_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Intel CHT Whiskey Cove PMIC operation region driver");
|
||||
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -18,7 +18,6 @@
|
|||
#include <linux/mfd/axp20x.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/iio/consumer.h>
|
||||
#include "intel_pmic.h"
|
||||
|
||||
#define XPOWER_GPADC_LOW 0x5b
|
||||
|
@ -186,28 +185,16 @@ static int intel_xpower_pmic_update_power(struct regmap *regmap, int reg,
|
|||
* @regmap: regmap of the PMIC device
|
||||
* @reg: register to get the reading
|
||||
*
|
||||
* We could get the sensor value by manipulating the HW regs here, but since
|
||||
* the axp288 IIO driver may also access the same regs at the same time, the
|
||||
* APIs provided by IIO subsystem are used here instead to avoid problems. As
|
||||
* a result, the two passed in params are of no actual use.
|
||||
*
|
||||
* Return a positive value on success, errno on failure.
|
||||
*/
|
||||
static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg)
|
||||
{
|
||||
struct iio_channel *gpadc_chan;
|
||||
int ret, val;
|
||||
u8 buf[2];
|
||||
|
||||
gpadc_chan = iio_channel_get(NULL, "axp288-system-temp");
|
||||
if (IS_ERR_OR_NULL(gpadc_chan))
|
||||
return -EACCES;
|
||||
if (regmap_bulk_read(regmap, AXP288_GP_ADC_H, buf, 2))
|
||||
return -EIO;
|
||||
|
||||
ret = iio_read_channel_raw(gpadc_chan, &val);
|
||||
if (ret < 0)
|
||||
val = ret;
|
||||
|
||||
iio_channel_release(gpadc_chan);
|
||||
return val;
|
||||
return (buf[0] << 4) + ((buf[1] >> 4) & 0x0F);
|
||||
}
|
||||
|
||||
static struct intel_pmic_opregion_data intel_xpower_pmic_opregion_data = {
|
||||
|
|
|
@ -103,6 +103,7 @@ struct cppc_perf_caps {
|
|||
u32 highest_perf;
|
||||
u32 nominal_perf;
|
||||
u32 lowest_perf;
|
||||
u32 lowest_nonlinear_perf;
|
||||
};
|
||||
|
||||
struct cppc_perf_ctrls {
|
||||
|
@ -115,7 +116,7 @@ struct cppc_perf_fb_ctrs {
|
|||
u64 reference;
|
||||
u64 delivered;
|
||||
u64 reference_perf;
|
||||
u64 ctr_wrap_time;
|
||||
u64 wraparound_time;
|
||||
};
|
||||
|
||||
/* Per CPU container for runtime CPPC management. */
|
||||
|
|
Loading…
Reference in a new issue