scsi: fdomain: Add register definitions
Add register bit definitions from documentation to header file and use them instead of magic constants. No changes to generated binary. Signed-off-by: Ondrej Zary <linux@zary.sk> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>alistair/sunxi64-5.4-dsi
Ondrej Zary
Martin K. Petersen
parent
aa343c695a
commit
1697c6a64c
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@ -99,7 +99,7 @@
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* up the machine.
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*/
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#define FIFO_COUNT 2 /* Number of 512 byte blocks before INTR */
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#define PARITY_MASK 0x08 /* Parity enabled, 0x00 = disabled */
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#define PARITY_MASK ACTL_PAREN /* Parity enabled, 0 = disabled */
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enum chip_type {
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unknown = 0x00,
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@ -117,18 +117,19 @@ struct fdomain {
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static inline void fdomain_make_bus_idle(struct fdomain *fd)
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{
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outb(0, fd->base + SCSI_Cntl);
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outb(0, fd->base + SCSI_Mode_Cntl);
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outb(0, fd->base + REG_BCTL);
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outb(0, fd->base + REG_MCTL);
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if (fd->chip == tmc18c50 || fd->chip == tmc18c30)
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/* Clear forced intr. */
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outb(0x21 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_RESET | ACTL_CLRFIRQ | PARITY_MASK,
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fd->base + REG_ACTL);
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else
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outb(0x01 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_RESET | PARITY_MASK, fd->base + REG_ACTL);
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}
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static enum chip_type fdomain_identify(int port)
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{
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u16 id = inb(port + LSB_ID_Code) | inb(port + MSB_ID_Code) << 8;
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u16 id = inb(port + REG_ID_LSB) | inb(port + REG_ID_MSB) << 8;
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switch (id) {
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case 0x6127:
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@ -140,10 +141,10 @@ static enum chip_type fdomain_identify(int port)
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}
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/* Try to toggle 32-bit mode. This only works on an 18c30 chip. */
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outb(0x80, port + IO_Control);
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if ((inb(port + Configuration2) & 0x80) == 0x80) {
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outb(0x00, port + IO_Control);
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if ((inb(port + Configuration2) & 0x80) == 0x00)
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outb(CFG2_32BIT, port + REG_CFG2);
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if ((inb(port + REG_CFG2) & CFG2_32BIT)) {
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outb(0, port + REG_CFG2);
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if ((inb(port + REG_CFG2) & CFG2_32BIT) == 0)
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return tmc18c30;
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}
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/* If that failed, we are an 18c50. */
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@ -155,8 +156,8 @@ static int fdomain_test_loopback(int base)
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int i;
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for (i = 0; i < 255; i++) {
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outb(i, base + Write_Loopback);
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if (inb(base + Read_Loopback) != i)
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outb(i, base + REG_LOOPBACK);
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if (inb(base + REG_LOOPBACK) != i)
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return 1;
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}
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@ -165,12 +166,12 @@ static int fdomain_test_loopback(int base)
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static void fdomain_reset(int base)
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{
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outb(1, base + SCSI_Cntl);
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outb(1, base + REG_BCTL);
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mdelay(20);
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outb(0, base + SCSI_Cntl);
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outb(0, base + REG_BCTL);
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mdelay(1150);
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outb(0, base + SCSI_Mode_Cntl);
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outb(PARITY_MASK, base + TMC_Cntl);
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outb(0, base + REG_MCTL);
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outb(PARITY_MASK, base + REG_ACTL);
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}
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static int fdomain_select(struct Scsi_Host *sh, int target)
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@ -179,20 +180,20 @@ static int fdomain_select(struct Scsi_Host *sh, int target)
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unsigned long timeout;
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struct fdomain *fd = shost_priv(sh);
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outb(0x82, fd->base + SCSI_Cntl); /* Bus Enable + Select */
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outb(BIT(sh->this_id) | BIT(target), fd->base + SCSI_Data_NoACK);
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outb(BCTL_BUSEN | BCTL_SEL, fd->base + REG_BCTL);
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outb(BIT(sh->this_id) | BIT(target), fd->base + REG_SCSI_DATA_NOACK);
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/* Stop arbitration and enable parity */
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outb(PARITY_MASK, fd->base + TMC_Cntl);
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outb(PARITY_MASK, fd->base + REG_ACTL);
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timeout = 350; /* 350 msec */
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do {
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status = inb(fd->base + SCSI_Status); /* Read adapter status */
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if (status & 1) { /* Busy asserted */
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status = inb(fd->base + REG_BSTAT);
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if (status & BSTAT_BSY) {
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/* Enable SCSI Bus */
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/* (on error, should make bus idle with 0) */
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outb(0x80, fd->base + SCSI_Cntl);
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outb(BCTL_BUSEN, fd->base + REG_BCTL);
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return 0;
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}
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mdelay(1);
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@ -203,7 +204,7 @@ static int fdomain_select(struct Scsi_Host *sh, int target)
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static void fdomain_finish_cmd(struct fdomain *fd, int result)
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{
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outb(0x00, fd->base + Interrupt_Cntl);
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outb(0, fd->base + REG_ICTL);
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fdomain_make_bus_idle(fd);
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fd->cur_cmd->result = result;
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fd->cur_cmd->scsi_done(fd->cur_cmd);
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@ -216,15 +217,15 @@ static void fdomain_read_data(struct scsi_cmnd *cmd)
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unsigned char *virt, *ptr;
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size_t offset, len;
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while ((len = inw(fd->base + FIFO_Data_Count)) > 0) {
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while ((len = inw(fd->base + REG_FIFO_COUNT)) > 0) {
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offset = scsi_bufflen(cmd) - scsi_get_resid(cmd);
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virt = scsi_kmap_atomic_sg(scsi_sglist(cmd), scsi_sg_count(cmd),
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&offset, &len);
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ptr = virt + offset;
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if (len & 1)
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*ptr++ = inb(fd->base + Read_FIFO);
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*ptr++ = inb(fd->base + REG_FIFO);
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if (len > 1)
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insw(fd->base + Read_FIFO, ptr, len >> 1);
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insw(fd->base + REG_FIFO, ptr, len >> 1);
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scsi_set_resid(cmd, scsi_get_resid(cmd) - len);
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scsi_kunmap_atomic_sg(virt);
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}
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@ -238,7 +239,7 @@ static void fdomain_write_data(struct scsi_cmnd *cmd)
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unsigned char *virt, *ptr;
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size_t offset, len;
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while ((len = FIFO_Size - inw(fd->base + FIFO_Data_Count)) > 512) {
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while ((len = FIFO_Size - inw(fd->base + REG_FIFO_COUNT)) > 512) {
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offset = scsi_bufflen(cmd) - scsi_get_resid(cmd);
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if (len + offset > scsi_bufflen(cmd)) {
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len = scsi_bufflen(cmd) - offset;
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@ -249,9 +250,9 @@ static void fdomain_write_data(struct scsi_cmnd *cmd)
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&offset, &len);
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ptr = virt + offset;
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if (len & 1)
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outb(*ptr++, fd->base + Write_FIFO);
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outb(*ptr++, fd->base + REG_FIFO);
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if (len > 1)
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outsw(fd->base + Write_FIFO, ptr, len >> 1);
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outsw(fd->base + REG_FIFO, ptr, len >> 1);
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scsi_set_resid(cmd, scsi_get_resid(cmd) - len);
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scsi_kunmap_atomic_sg(virt);
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}
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@ -270,66 +271,68 @@ static void fdomain_work(struct work_struct *work)
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spin_lock_irqsave(sh->host_lock, flags);
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if (cmd->SCp.phase & in_arbitration) {
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status = inb(fd->base + TMC_Status);
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if (!(status & 0x02)) {
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status = inb(fd->base + REG_ASTAT);
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if (!(status & ASTAT_ARB)) {
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fdomain_finish_cmd(fd, DID_BUS_BUSY << 16);
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goto out;
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}
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cmd->SCp.phase = in_selection;
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outb(0x40 | FIFO_COUNT, fd->base + Interrupt_Cntl);
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outb(0x82, fd->base + SCSI_Cntl); /* Bus Enable + Select */
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outb(BIT(cmd->device->host->this_id) |
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BIT(scmd_id(cmd)), fd->base + SCSI_Data_NoACK);
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outb(ICTL_SEL | FIFO_COUNT, fd->base + REG_ICTL);
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outb(BCTL_BUSEN | BCTL_SEL, fd->base + REG_BCTL);
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outb(BIT(cmd->device->host->this_id) | BIT(scmd_id(cmd)),
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fd->base + REG_SCSI_DATA_NOACK);
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/* Stop arbitration and enable parity */
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outb(0x10 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL);
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goto out;
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} else if (cmd->SCp.phase & in_selection) {
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status = inb(fd->base + SCSI_Status);
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if (!(status & 0x01)) {
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status = inb(fd->base + REG_BSTAT);
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if (!(status & BSTAT_BSY)) {
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/* Try again, for slow devices */
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if (fdomain_select(cmd->device->host, scmd_id(cmd))) {
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fdomain_finish_cmd(fd, DID_NO_CONNECT << 16);
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goto out;
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}
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/* Stop arbitration and enable parity */
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outb(0x10 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL);
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}
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cmd->SCp.phase = in_other;
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outb(0x90 | FIFO_COUNT, fd->base + Interrupt_Cntl);
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outb(0x80, fd->base + SCSI_Cntl);
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outb(ICTL_FIFO | ICTL_REQ | FIFO_COUNT, fd->base + REG_ICTL);
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outb(BCTL_BUSEN, fd->base + REG_BCTL);
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goto out;
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}
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/* cur_cmd->SCp.phase == in_other: this is the body of the routine */
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status = inb(fd->base + SCSI_Status);
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status = inb(fd->base + REG_BSTAT);
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if (status & 0x10) { /* REQ */
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if (status & BSTAT_REQ) {
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switch (status & 0x0e) {
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case 0x08: /* COMMAND OUT */
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case BSTAT_CMD: /* COMMAND OUT */
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outb(cmd->cmnd[cmd->SCp.sent_command++],
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fd->base + Write_SCSI_Data);
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fd->base + REG_SCSI_DATA);
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break;
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case 0x00: /* DATA OUT -- tmc18c50/tmc18c30 only */
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case 0: /* DATA OUT -- tmc18c50/tmc18c30 only */
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if (fd->chip != tmc1800 && !cmd->SCp.have_data_in) {
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cmd->SCp.have_data_in = -1;
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outb(0xd0 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | ACTL_FIFOWR | ACTL_FIFOEN |
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PARITY_MASK, fd->base + REG_ACTL);
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}
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break;
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case 0x04: /* DATA IN -- tmc18c50/tmc18c30 only */
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case BSTAT_IO: /* DATA IN -- tmc18c50/tmc18c30 only */
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if (fd->chip != tmc1800 && !cmd->SCp.have_data_in) {
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cmd->SCp.have_data_in = 1;
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outb(0x90 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | ACTL_FIFOEN | PARITY_MASK,
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fd->base + REG_ACTL);
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}
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break;
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case 0x0c: /* STATUS IN */
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cmd->SCp.Status = inb(fd->base + Read_SCSI_Data);
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case BSTAT_CMD | BSTAT_IO: /* STATUS IN */
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cmd->SCp.Status = inb(fd->base + REG_SCSI_DATA);
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break;
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case 0x0a: /* MESSAGE OUT */
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outb(MESSAGE_REJECT, fd->base + Write_SCSI_Data);
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case BSTAT_MSG | BSTAT_CMD: /* MESSAGE OUT */
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outb(MESSAGE_REJECT, fd->base + REG_SCSI_DATA);
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break;
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case 0x0e: /* MESSAGE IN */
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cmd->SCp.Message = inb(fd->base + Read_SCSI_Data);
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case BSTAT_MSG | BSTAT_IO | BSTAT_CMD: /* MESSAGE IN */
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cmd->SCp.Message = inb(fd->base + REG_SCSI_DATA);
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if (!cmd->SCp.Message)
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++done;
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break;
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@ -340,10 +343,12 @@ static void fdomain_work(struct work_struct *work)
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cmd->SCp.sent_command >= cmd->cmd_len) {
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if (cmd->sc_data_direction == DMA_TO_DEVICE) {
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cmd->SCp.have_data_in = -1;
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outb(0xd0 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | ACTL_FIFOWR | ACTL_FIFOEN |
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PARITY_MASK, fd->base + REG_ACTL);
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} else {
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cmd->SCp.have_data_in = 1;
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outb(0x90 | PARITY_MASK, fd->base + TMC_Cntl);
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outb(ACTL_IRQEN | ACTL_FIFOEN | PARITY_MASK,
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fd->base + REG_ACTL);
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}
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}
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@ -359,10 +364,12 @@ static void fdomain_work(struct work_struct *work)
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(DID_OK << 16));
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} else {
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if (cmd->SCp.phase & disconnect) {
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outb(0xd0 | FIFO_COUNT, fd->base + Interrupt_Cntl);
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outb(0x00, fd->base + SCSI_Cntl);
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outb(ICTL_FIFO | ICTL_SEL | ICTL_REQ | FIFO_COUNT,
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fd->base + REG_ICTL);
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outb(0, fd->base + REG_BCTL);
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} else
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outb(0x90 | FIFO_COUNT, fd->base + Interrupt_Cntl);
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outb(ICTL_FIFO | ICTL_REQ | FIFO_COUNT,
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fd->base + REG_ICTL);
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}
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out:
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spin_unlock_irqrestore(sh->host_lock, flags);
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@ -373,10 +380,10 @@ static irqreturn_t fdomain_irq(int irq, void *dev_id)
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struct fdomain *fd = dev_id;
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/* Is it our IRQ? */
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if ((inb(fd->base + TMC_Status) & 0x01) == 0)
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if ((inb(fd->base + REG_ASTAT) & ASTAT_IRQ) == 0)
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return IRQ_NONE;
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outb(0x00, fd->base + Interrupt_Cntl);
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outb(0, fd->base + REG_ICTL);
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/* We usually have one spurious interrupt after each command. */
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if (!fd->cur_cmd) /* Spurious interrupt */
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@ -406,12 +413,13 @@ static int fdomain_queue(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
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fdomain_make_bus_idle(fd);
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/* Start arbitration */
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outb(0x00, fd->base + Interrupt_Cntl);
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outb(0x00, fd->base + SCSI_Cntl); /* Disable data drivers */
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outb(BIT(cmd->device->host->this_id),
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fd->base + SCSI_Data_NoACK); /* Set our id bit */
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outb(0x20, fd->base + Interrupt_Cntl);
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outb(0x14 | PARITY_MASK, fd->base + TMC_Cntl); /* Start arbitration */
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outb(0, fd->base + REG_ICTL);
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outb(0, fd->base + REG_BCTL); /* Disable data drivers */
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/* Set our id bit */
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outb(BIT(cmd->device->host->this_id), fd->base + REG_SCSI_DATA_NOACK);
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outb(ICTL_ARB, fd->base + REG_ICTL);
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/* Start arbitration */
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outb(ACTL_ARB | ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL);
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spin_unlock_irqrestore(sh->host_lock, flags);
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@ -12,34 +12,95 @@ enum {
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sent_ident = 0x40,
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};
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enum in_port_type {
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Read_SCSI_Data = 0,
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SCSI_Status = 1,
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TMC_Status = 2,
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FIFO_Status = 3, /* tmc18c50/tmc18c30 only */
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Interrupt_Cond = 4, /* tmc18c50/tmc18c30 only */
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LSB_ID_Code = 5,
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MSB_ID_Code = 6,
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Read_Loopback = 7,
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SCSI_Data_NoACK = 8,
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Interrupt_Status = 9,
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Configuration1 = 10,
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Configuration2 = 11, /* tmc18c50/tmc18c30 only */
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Read_FIFO = 12,
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FIFO_Data_Count = 14
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};
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enum out_port_type {
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Write_SCSI_Data = 0,
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SCSI_Cntl = 1,
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Interrupt_Cntl = 2,
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SCSI_Mode_Cntl = 3,
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TMC_Cntl = 4,
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Memory_Cntl = 5, /* tmc18c50/tmc18c30 only */
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Write_Loopback = 7,
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IO_Control = 11, /* tmc18c30 only */
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Write_FIFO = 12
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};
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/* (@) = not present on TMC1800, (#) = not present on TMC1800 and TMC18C50 */
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#define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
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#define REG_BSTAT 1 /* R: SCSI Bus Status */
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#define BSTAT_BSY BIT(0) /* Busy */
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#define BSTAT_MSG BIT(1) /* Message */
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#define BSTAT_IO BIT(2) /* Input/Output */
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#define BSTAT_CMD BIT(3) /* Command/Data */
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#define BSTAT_REQ BIT(4) /* Request and Not Ack */
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#define BSTAT_SEL BIT(5) /* Select */
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#define BSTAT_ACK BIT(6) /* Acknowledge and Request */
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#define BSTAT_ATN BIT(7) /* Attention */
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#define REG_BCTL 1 /* W: SCSI Bus Control */
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#define BCTL_RST BIT(0) /* Bus Reset */
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#define BCTL_SEL BIT(1) /* Select */
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#define BCTL_BSY BIT(2) /* Busy */
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#define BCTL_ATN BIT(3) /* Attention */
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#define BCTL_IO BIT(4) /* Input/Output */
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#define BCTL_CMD BIT(5) /* Command/Data */
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#define BCTL_MSG BIT(6) /* Message */
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#define BCTL_BUSEN BIT(7) /* Enable bus drivers */
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#define REG_ASTAT 2 /* R: Adapter Status 1 */
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#define ASTAT_IRQ BIT(0) /* Interrupt active */
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#define ASTAT_ARB BIT(1) /* Arbitration complete */
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#define ASTAT_PARERR BIT(2) /* Parity error */
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#define ASTAT_RST BIT(3) /* SCSI reset occurred */
|
||||
#define ASTAT_FIFODIR BIT(4) /* FIFO direction */
|
||||
#define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
|
||||
#define ASTAT_PAREN BIT(6) /* Parity enabled */
|
||||
#define ASTAT_BUSEN BIT(7) /* Bus drivers enabled */
|
||||
#define REG_ICTL 2 /* W: Interrupt Control */
|
||||
#define ICTL_FIFO_MASK 0x0f /* FIFO threshold, 1/16 FIFO size */
|
||||
#define ICTL_FIFO BIT(4) /* Int. on FIFO count */
|
||||
#define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
|
||||
#define ICTL_SEL BIT(6) /* Int. on SCSI Select */
|
||||
#define ICTL_REQ BIT(7) /* Int. on SCSI Request */
|
||||
#define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
|
||||
#define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
|
||||
#define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */
|
||||
#define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */
|
||||
#define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */
|
||||
#define REG_MCTL 3 /* W: SCSI Data Mode Control */
|
||||
#define MCTL_ACK_MASK 0x0f /* Acknowledge period */
|
||||
#define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
|
||||
#define MCTL_TARGET BIT(5) /* Enable target mode */
|
||||
#define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
|
||||
#define MCTL_SYNC BIT(7) /* Enable Synchronous */
|
||||
#define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
|
||||
#define IRQ_FIFO BIT(1) /* FIFO interrupt */
|
||||
#define IRQ_REQ BIT(2) /* SCSI Request interrupt */
|
||||
#define IRQ_SEL BIT(3) /* SCSI Select interrupt */
|
||||
#define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */
|
||||
#define IRQ_RST BIT(5) /* SCSI Reset interrupt */
|
||||
#define IRQ_FORCED BIT(6) /* Forced interrupt */
|
||||
#define IRQ_TIMEOUT BIT(7) /* Bus timeout */
|
||||
#define REG_ACTL 4 /* W: Adapter Control 1 */
|
||||
#define ACTL_RESET BIT(0) /* Reset FIFO, parity, reset int. */
|
||||
#define ACTL_FIRQ BIT(1) /* Set Forced interrupt */
|
||||
#define ACTL_ARB BIT(2) /* Initiate Bus Arbitration */
|
||||
#define ACTL_PAREN BIT(3) /* Enable SCSI Parity */
|
||||
#define ACTL_IRQEN BIT(4) /* Enable interrupts */
|
||||
#define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */
|
||||
#define ACTL_FIFOWR BIT(6) /* FIFO Direction (1=write) */
|
||||
#define ACTL_FIFOEN BIT(7) /* Enable FIFO */
|
||||
#define REG_ID_LSB 5 /* R: ID Code (LSB) */
|
||||
#define REG_ACTL2 5 /* Adapter Control 2 - (@) */
|
||||
#define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */
|
||||
#define ACTL2_SLEEP BIT(7) /* Sleep mode */
|
||||
#define REG_ID_MSB 6 /* R: ID Code (MSB) */
|
||||
#define REG_LOOPBACK 7 /* R/W: Loopback */
|
||||
#define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
|
||||
#define REG_ASTAT3 9 /* R: Adapter Status 3 */
|
||||
#define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */
|
||||
#define ASTAT3_RAMOVRLY BIT(1) /* RAM overlay enabled */
|
||||
#define ASTAT3_TARGERR BIT(2) /* Target error */
|
||||
#define ASTAT3_IRQEN BIT(3) /* Interrupts enabled */
|
||||
#define ASTAT3_IRQMASK 0xf0 /* Enabled interrupts mask */
|
||||
#define REG_CFG1 10 /* R: Configuration Register 1 */
|
||||
#define CFG1_BUS BIT(0) /* 0 = ISA */
|
||||
#define CFG1_IRQ_MASK 0x0e /* IRQ jumpers */
|
||||
#define CFG1_IO_MASK 0x30 /* I/O base jumpers */
|
||||
#define CFG1_BIOS_MASK 0xc0 /* BIOS base jumpers */
|
||||
#define REG_CFG2 11 /* R/W: Configuration Register 2 (@) */
|
||||
#define CFG2_ROMDIS BIT(0) /* ROM disabled */
|
||||
#define CFG2_RAMDIS BIT(1) /* RAM disabled */
|
||||
#define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */
|
||||
#define CFG2_NOWS BIT(3) /* No wait states */
|
||||
#define CFG2_32BIT BIT(7) /* 32-bit mode */
|
||||
#define REG_FIFO 12 /* R/W: FIFO */
|
||||
#define REG_FIFO_COUNT 14 /* R: FIFO Data Count */
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static const struct dev_pm_ops fdomain_pm_ops;
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ static int fdomain_isa_match(struct device *dev, unsigned int ndev)
|
|||
if (!request_region(base, FDOMAIN_REGION_SIZE, "fdomain_isa"))
|
||||
return 0;
|
||||
|
||||
irq = irqs[(inb(base + Configuration1) & 0x0e) >> 1];
|
||||
irq = irqs[(inb(base + REG_CFG1) & 0x0e) >> 1];
|
||||
|
||||
|
||||
if (sig)
|
||||
|
|
@ -164,7 +164,7 @@ static int fdomain_isa_param_match(struct device *dev, unsigned int ndev)
|
|||
}
|
||||
|
||||
if (irq_ <= 0)
|
||||
irq_ = irqs[(inb(io[ndev] + Configuration1) & 0x0e) >> 1];
|
||||
irq_ = irqs[(inb(io[ndev] + REG_CFG1) & 0x0e) >> 1];
|
||||
|
||||
sh = fdomain_create(io[ndev], irq_, scsi_id[ndev], dev);
|
||||
if (!sh) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue