MIPS: Delete Wind River ppmc eval board support.
This board has been EOL for many years now; lets not burden people doing build coverage and other tree wide work with working on essentially dead files. [ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Patchwork: http://patchwork.linux-mips.org/patch/5503/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Paul Gortmaker
Ralf Baechle
parent
5a772eee55
commit
169c3c164f
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@ -30,7 +30,6 @@ platforms += sibyte
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platforms += sni
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platforms += txx9
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platforms += vr41xx
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platforms += wrppmc
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# include the platform specific files
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include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
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@ -712,29 +712,6 @@ config MIKROTIK_RB532
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Support the Mikrotik(tm) RouterBoard 532 series,
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based on the IDT RC32434 SoC.
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config WR_PPMC
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bool "Wind River PPMC board"
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select CEVT_R4K
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select CSRC_R4K
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select IRQ_CPU
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select BOOT_ELF32
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select PCI_GT64XXX_PCI0
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_NEVADA
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select SYS_HAS_CPU_RM7000
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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help
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This enables support for the Wind River MIPS32 4KC PPMC evaluation
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board, which is based on GT64120 bridge chip.
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config CAVIUM_OCTEON_SOC
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bool "Cavium Networks Octeon SoC based boards"
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select CEVT_R4K
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@ -1,97 +0,0 @@
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CONFIG_WR_PPMC=y
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CONFIG_HZ_1000=y
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CONFIG_EXPERIMENTAL=y
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# CONFIG_SWAP is not set
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CONFIG_SYSVIPC=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_BLK_DEV_INITRD=y
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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CONFIG_EXPERT=y
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CONFIG_KALLSYMS_EXTRA_PASS=y
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# CONFIG_EPOLL is not set
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODVERSIONS=y
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CONFIG_MODULE_SRCVERSION_ALL=y
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CONFIG_PCI=y
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CONFIG_HOTPLUG_PCI=y
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CONFIG_BINFMT_MISC=y
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CONFIG_PM=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_XFRM_MIGRATE=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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CONFIG_IP_PNP_RARP=y
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CONFIG_IP_MROUTE=y
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CONFIG_ARPD=y
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CONFIG_INET_XFRM_MODE_TRANSPORT=m
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CONFIG_INET_XFRM_MODE_TUNNEL=m
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CONFIG_INET_XFRM_MODE_BEET=m
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CONFIG_TCP_MD5SIG=y
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# CONFIG_IPV6 is not set
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CONFIG_NETWORK_SECMARK=y
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CONFIG_FW_LOADER=m
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CONFIG_BLK_DEV_RAM=y
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CONFIG_SGI_IOC4=m
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CONFIG_NETDEVICES=y
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CONFIG_PHYLIB=y
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CONFIG_VITESSE_PHY=m
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CONFIG_SMSC_PHY=m
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CONFIG_NET_ETHERNET=y
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CONFIG_NET_PCI=y
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CONFIG_E100=y
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CONFIG_QLA3XXX=m
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CONFIG_CHELSIO_T3=m
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CONFIG_NETXEN_NIC=m
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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# CONFIG_HW_RANDOM is not set
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CONFIG_PROC_KCORE=y
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CONFIG_TMPFS=y
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CONFIG_TMPFS_POSIX_ACL=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3=y
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CONFIG_ROOT_NFS=y
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CONFIG_DLM=m
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="console=ttyS0,115200n8"
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CONFIG_CRYPTO_NULL=m
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CONFIG_CRYPTO_CBC=m
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CONFIG_CRYPTO_ECB=m
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CONFIG_CRYPTO_LRW=m
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CONFIG_CRYPTO_PCBC=m
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CONFIG_CRYPTO_XCBC=m
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CONFIG_CRYPTO_MD4=m
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CONFIG_CRYPTO_MICHAEL_MIC=m
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CONFIG_CRYPTO_SHA256=m
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CONFIG_CRYPTO_SHA512=m
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CONFIG_CRYPTO_TGR192=m
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CONFIG_CRYPTO_WP512=m
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CONFIG_CRYPTO_ANUBIS=m
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CONFIG_CRYPTO_ARC4=m
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CONFIG_CRYPTO_BLOWFISH=m
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CONFIG_CRYPTO_CAMELLIA=m
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CONFIG_CRYPTO_CAST5=m
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CONFIG_CRYPTO_CAST6=m
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CONFIG_CRYPTO_DES=m
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CONFIG_CRYPTO_FCRYPT=m
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CONFIG_CRYPTO_KHAZAD=m
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CONFIG_CRYPTO_SERPENT=m
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CONFIG_CRYPTO_TEA=m
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CONFIG_CRYPTO_TWOFISH=m
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CONFIG_CRYPTO_DEFLATE=m
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CONFIG_CRC_CCITT=y
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CONFIG_CRC16=y
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CONFIG_LIBCRC32C=y
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@ -1,83 +0,0 @@
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/*
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* This is a direct copy of the ev96100.h file, with a global
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* search and replace. The numbers are the same.
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*
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* The reason I'm duplicating this is so that the 64120/96100
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* defines won't be confusing in the source code.
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*/
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#ifndef __ASM_MIPS_GT64120_H
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#define __ASM_MIPS_GT64120_H
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/*
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* This is the CPU physical memory map of PPMC Board:
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*
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* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
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* 0x1C000000-0x1C000000 - LED (CS0)
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* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
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* 0x1F000000-0x1F000000 - MailBox (CS3)
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* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
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*/
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#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
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#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
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#define WRPPMC_UART16550_BASE 0x1C800000
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#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
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#define WRPPMC_LED_BASE 0x1C000000
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#define WRPPMC_MBOX_BASE 0x1F000000
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#define WRPPMC_BOOTROM_BASE 0x1FC00000
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#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
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#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
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#define WRPPMC_UART16550_IRQ 6
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#define WRPPMC_PCI_INTA_IRQ 3
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/*
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* PCI Bus I/O and Memory resources allocation
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*
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* NOTE: We only have PCI_0 hose interface
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*/
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#define GT_PCI_MEM_BASE 0x13000000UL
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#define GT_PCI_MEM_SIZE 0x02000000UL
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#define GT_PCI_IO_BASE 0x11000000UL
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#define GT_PCI_IO_SIZE 0x02000000UL
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/*
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* PCI interrupts will come in on either the INTA or INTD interrupt lines,
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* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
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* boards, they all either come in on IntD or they all come in on IntA, they
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* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
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* "requested" interrupt numbers and go through the list whenever we get an
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* IntA/D.
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*
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* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
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* INTD is 11.
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*/
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#define GT_TIMER 4
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#define GT_INTA 2
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#define GT_INTD 5
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#ifndef __ASSEMBLY__
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/*
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* GT64120 internal register space base address
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*/
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extern unsigned long gt64120_base;
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#define GT64120_BASE (gt64120_base)
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/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
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#undef WRPPMC_EARLY_DEBUG
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#ifdef WRPPMC_EARLY_DEBUG
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extern void wrppmc_led_on(int mask);
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extern void wrppmc_led_off(int mask);
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extern void wrppmc_early_printk(const char *fmt, ...);
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#else
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#define wrppmc_early_printk(fmt, ...) do {} while (0)
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#endif /* WRPPMC_EARLY_DEBUG */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_MIPS_GT64120_H */
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@ -1,24 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
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#define __ASM_MIPS_MACH_WRPPMC_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
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@ -52,7 +52,6 @@ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
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obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
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obj-$(CONFIG_CPU_XLR) += pci-xlr.o
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@ -1,37 +0,0 @@
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/*
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* fixup-wrppmc.c: PPMC board specific PCI fixup
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/gt64120.h>
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/* PCI interrupt pins */
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#define PCI_INTA 1
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#define PCI_INTB 2
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#define PCI_INTC 3
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#define PCI_INTD 4
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#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
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static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
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/* 0 INTA INTB INTC INTD */
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[0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
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[6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return pci_irq_tab[slot][pin];
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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@ -1,12 +0,0 @@
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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# Copyright 2006 Wind River System, Inc.
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# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
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#
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# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
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#
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obj-y += irq.o pci.o reset.o serial.o setup.o time.o
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@ -1,7 +0,0 @@
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#
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# Wind River PPMC Board (4KC + GT64120)
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#
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platform-$(CONFIG_WR_PPMC) += wrppmc/
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cflags-$(CONFIG_WR_PPMC) += \
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-I$(srctree)/arch/mips/include/asm/mach-wrppmc
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load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
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@ -1,56 +0,0 @@
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/*
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* irq.c: GT64120 Interrupt Controller
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*
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* Copyright (C) 2006, Wind River System Inc.
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* Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/gt64120.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
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else if (pending & STATUSF_IP6)
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do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
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else if (pending & STATUSF_IP3)
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do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
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else
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spurious_interrupt();
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}
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/**
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* Initialize GT64120 Interrupt Controller
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*/
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void gt64120_init_pic(void)
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{
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/* clear CPU Interrupt Cause Registers */
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GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
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GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
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/* Disable all interrupts from GT64120 bridge chip */
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GT_WRITE(GT_INTRMASK_OFS, 0x00);
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GT_WRITE(GT_HINTRMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
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GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
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}
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void __init arch_init_irq(void)
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{
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/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
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mips_cpu_irq_init();
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gt64120_init_pic();
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}
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@ -1,52 +0,0 @@
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/*
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* pci.c: GT64120 PCI support.
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*
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* Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/gt64120.h>
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extern struct pci_ops gt64xxx_pci0_ops;
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static struct resource pci0_io_resource = {
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.name = "pci_0 io",
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.start = GT_PCI_IO_BASE,
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.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci0_mem_resource = {
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.name = "pci_0 memory",
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.start = GT_PCI_MEM_BASE,
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.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller hose_0 = {
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.pci_ops = >64xxx_pci0_ops,
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.io_resource = &pci0_io_resource,
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.mem_resource = &pci0_mem_resource,
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};
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static int __init gt64120_pci_init(void)
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{
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(void) GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
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(void) GT_READ(GT_PCI0_BARE_OFS);
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/* reset the whole PCI I/O space range */
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ioport_resource.start = GT_PCI_IO_BASE;
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ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
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register_pci_controller(&hose_0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(gt64120_pci_init);
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1997 Ralf Baechle
|
||||
*/
|
||||
#include <linux/irqflags.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
void wrppmc_machine_restart(char *command)
|
||||
{
|
||||
/*
|
||||
* Ouch, we're still alive ... This time we take the silver bullet ...
|
||||
* ... and find that we leave the hardware in a state in which the
|
||||
* kernel in the flush locks up somewhen during of after the PCI
|
||||
* detection stuff.
|
||||
*/
|
||||
local_irq_disable();
|
||||
set_c0_status(ST0_BEV | ST0_ERL);
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
|
||||
flush_cache_all();
|
||||
write_c0_wired(0);
|
||||
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
||||
}
|
||||
|
||||
void wrppmc_machine_halt(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
|
||||
printk(KERN_NOTICE "You can safely turn off the power\n");
|
||||
while (1) {
|
||||
if (cpu_wait)
|
||||
cpu_wait();
|
||||
}
|
||||
}
|
||||
|
|
@ -1,80 +0,0 @@
|
|||
/*
|
||||
* Registration of WRPPMC UART platform device.
|
||||
*
|
||||
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
static struct resource wrppmc_uart_resource[] __initdata = {
|
||||
{
|
||||
.start = WRPPMC_UART16550_BASE,
|
||||
.end = WRPPMC_UART16550_BASE + 7,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = WRPPMC_UART16550_IRQ,
|
||||
.end = WRPPMC_UART16550_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port wrppmc_serial8250_port[] = {
|
||||
{
|
||||
.irq = WRPPMC_UART16550_IRQ,
|
||||
.uartclk = WRPPMC_UART16550_CLOCK,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_IOREMAP | UPF_SKIP_TEST,
|
||||
.mapbase = WRPPMC_UART16550_BASE,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static __init int wrppmc_uart_add(void)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
int retval;
|
||||
|
||||
pdev = platform_device_alloc("serial8250", -1);
|
||||
if (!pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
pdev->id = PLAT8250_DEV_PLATFORM;
|
||||
pdev->dev.platform_data = wrppmc_serial8250_port;
|
||||
|
||||
retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
|
||||
ARRAY_SIZE(wrppmc_uart_resource));
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
retval = platform_device_add(pdev);
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_device:
|
||||
platform_device_put(pdev);
|
||||
|
||||
return retval;
|
||||
}
|
||||
device_initcall(wrppmc_uart_add);
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
/*
|
||||
* setup.c: Setup pointers to hardware dependent routines.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
unsigned long gt64120_base = KSEG1ADDR(0x14000000);
|
||||
|
||||
#ifdef WRPPMC_EARLY_DEBUG
|
||||
|
||||
static volatile unsigned char * wrppmc_led = \
|
||||
(volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
|
||||
|
||||
/*
|
||||
* PPMC LED control register:
|
||||
* -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
|
||||
* -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
|
||||
* -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
|
||||
*/
|
||||
void wrppmc_led_on(int mask)
|
||||
{
|
||||
unsigned char value = *wrppmc_led;
|
||||
|
||||
value &= (0xF8 | mask);
|
||||
*wrppmc_led = value;
|
||||
}
|
||||
|
||||
/* If mask = 0, turn off all LEDs */
|
||||
void wrppmc_led_off(int mask)
|
||||
{
|
||||
unsigned char value = *wrppmc_led;
|
||||
|
||||
value |= (0x7 & mask);
|
||||
*wrppmc_led = value;
|
||||
}
|
||||
|
||||
/*
|
||||
* We assume that bootloader has initialized UART16550 correctly
|
||||
*/
|
||||
void __init wrppmc_early_putc(char ch)
|
||||
{
|
||||
static volatile unsigned char *wrppmc_uart = \
|
||||
(volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
|
||||
unsigned char value;
|
||||
|
||||
/* Wait until Transmit-Holding-Register is empty */
|
||||
while (1) {
|
||||
value = *(wrppmc_uart + 5);
|
||||
if (value & 0x20)
|
||||
break;
|
||||
}
|
||||
|
||||
*wrppmc_uart = ch;
|
||||
}
|
||||
|
||||
void __init wrppmc_early_printk(const char *fmt, ...)
|
||||
{
|
||||
static char pbuf[256] = {'\0', };
|
||||
char *ch = pbuf;
|
||||
va_list args;
|
||||
unsigned int i;
|
||||
|
||||
memset(pbuf, 0, 256);
|
||||
va_start(args, fmt);
|
||||
i = vsprintf(pbuf, fmt, args);
|
||||
va_end(args);
|
||||
|
||||
/* Print the string */
|
||||
while (*ch != '\0') {
|
||||
wrppmc_early_putc(*ch);
|
||||
/* if print '\n', also print '\r' */
|
||||
if (*ch++ == '\n')
|
||||
wrppmc_early_putc('\r');
|
||||
}
|
||||
}
|
||||
#endif /* WRPPMC_EARLY_DEBUG */
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
extern void wrppmc_machine_restart(char *command);
|
||||
extern void wrppmc_machine_halt(void);
|
||||
|
||||
_machine_restart = wrppmc_machine_restart;
|
||||
_machine_halt = wrppmc_machine_halt;
|
||||
pm_power_off = wrppmc_machine_halt;
|
||||
|
||||
/* This makes the operations of 'in/out[bwl]' to the
|
||||
* physical address ( < KSEG0) can work via KSEG1
|
||||
*/
|
||||
set_io_port_base(KSEG1);
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Wind River PPMC (GT64120)";
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes basic routines and structures pointers, memory size (as
|
||||
* given by the bios and saves the command line.
|
||||
*/
|
||||
void __init prom_init(void)
|
||||
{
|
||||
add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
|
||||
add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
|
||||
|
||||
wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
|
||||
WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
|
||||
}
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*
|
||||
* time.c: MIPS CPU Count/Compare timer hookup
|
||||
*
|
||||
* Author: Mark.Zhan, <rongkai.zhan@windriver.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2006, Wind River System Inc.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/gt64120.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
|
||||
|
||||
/*
|
||||
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
|
||||
*
|
||||
* NOTE: We disable all GT64120 timers, and use MIPS processor internal
|
||||
* timer as the source of kernel clock tick.
|
||||
*/
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
/* Disable GT64120 timers */
|
||||
GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
|
||||
GT_WRITE(GT_TC0_OFS, 0x00);
|
||||
GT_WRITE(GT_TC1_OFS, 0x00);
|
||||
GT_WRITE(GT_TC2_OFS, 0x00);
|
||||
GT_WRITE(GT_TC3_OFS, 0x00);
|
||||
|
||||
/* Use MIPS compare/count internal timer */
|
||||
mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
|
||||
}
|
||||
Loading…
Reference in New Issue