drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -957,7 +957,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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/* WaDisablePartialResolveInVc:skl,bxt */
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WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
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/* WaCcsTlbPrefetchDisable:skl */
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/* WaCcsTlbPrefetchDisable:skl,bxt */
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WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
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GEN9_CCS_TLB_PREFETCH_ENABLE);
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